Sun Microsystems, Inc.

Oracle America, Inc.

Kurt J Goebel

Partha P Tirumalai

Spiros Kalogeropulos

Yonghong Song

Fu-Hwa Wang

Raj Prakash

A method and mechanism for producing and executing self-steering program code. A method comprises analyzing program code and identifying portions which may be amenable to optimization. Having identified such a portion of code, at least one optimized version of the identified code is added to the program code. Additionally, a selection mechanism is added to the program code which is configured to select between two or more versions of the portion of code during runtime. The modified program code is then compiled with the added optimized version and the selection mechanism. During execution, monitoring of behavior of the code may be enabled or disabled. Based upon such monitored behavior, a different version of the code may be selected for execution. Various optimized versions may be selected for execution in a manner which takes advantage of the current behavior of the program.

Adaptive code through self steered execution

Automatically executing commands to process code (e.g., compile commands, interpret commands, etc.) and recording code characteristic metric values (e.g., file size, execution time, etc.) allows automatic code tuning. The automatic turning system may execute predefined commands on codes, automatically intelligently build commands, both execute predefined commands and intelligently build upon those predefined commands, etc. With the automatic intelligent building of commands to build more effective commands, an automatic tuning system can efficiently and judiciously search through available code development tool options to find the more effective combinations of options to generate executable codes.

Automatic code tuning

One embodiment of the present invention provides a system that facilitates optimizing computer program performance by using steered execution. The system operates by first receiving source code for a computer program, and then compiling a portion of this source code with a first set of optimizations to generate a first compiled portion. The system also compiles the same portion of the source code with a second set of optimizations to generate a second compiled portion. Remaining source code is compiled to generate a third compiled portion. Additionally, a rule is generated for selecting between the first compiled portion and the second compiled portion. Finally, the first compiled portion, the second compiled portion, the third compiled portion, and the rule are combined into an executable output file.

Method and apparatus for optimizing computer program performance using steered execution

Platform independent processing of the source code is performed, such as lexical analysis, semantic analysis, syntax analysis, and platform independent optimization, and an intermediate representation of the source code is generated. This intermediate representation is carried forward into the next stage of processing, which is platform dependent processing. The intermediate representation undergoes machine specific analysis and an executable representation (i.e., executable code) of the source code for a particular platform is generated. However, the intermediate representation, which has not been converted to a machine specific representation, is included with the executable representation. The source code can essentially be ported to a different platform by extracting the intermediate representation and performing platform dependent processing on the intermediate representation. The extracted intermediate representation, which has already undergone platform independent processing, is processed for the target platform and an executable representation for the target platform is generated.

Portable executable source code representations

Apparatus, methods and computer program products are disclosed for a high level language compiler that includes a binary re-optimization capability. This re-optimization capability inputs a binary executable and outputs a binary module optimized for a target computer system. The binary module can be linked to create an optimized binary executable. This capability is provided by adding a front end segment to the compiler that reads the binary executable and creates an intermediate representation of the binary executable. This intermediate representation is normalized to remove prior optimization artifacts and to virtualize register usage. The intermediate representation is then optimized for a target computer system resulting in a binary module that can be linked to make a binary executable that is optimized for the target computer.

Method, apparatus and computer programmed product for binary re-optimization using a high level language compiler

Techniques for allocating registers when generating code is described. A snapshot is generated when generating code. The snapshot contains sufficient information to restore the state of generating code that existed at the point when the snapshot was generated so that the generation of code can proceed from that point. A first set of code optimizations is generated. In response to determining that the first set of code optimizations fails to meet efficiency criteria, the generation of code proceeds based on the snapshot without incorporating the first set of code optimizations. Feedback is generated by analyzing the allocation of registers based on the first set of code optimizations. A second set of code optimizations is based on the feedback. Feedback includes information such as the number of spills occurring based on the first set of code optimizations. In addition, an allocation of registers based on a second set of code optimizations is performed in parallel with an allocation of registers based on the first set of code optimizations. Generation of code proceeds based on the second set of code optimizations when the second set of code optimizations causes less spilling the first set of code optimizations.

Register resource allocation feedback

Program routines normally requiring windowed register allocation using conventional assembly code generation in a compiler are examined for eligibility for a wrapper routine optimization procedure in which wrapper routine assembly code instructions are generated in response to the application of high level programming language instructions specifying routines. If not eligible, the compiler generates assembly code instructions in a conventional way, allocating windowed registers to each routine. If the routine is eligible for wrapper routine optimization, the routine is further examined to determine whether the routine includes tail routine calls only or calls within the body of the routine. If the former, the routine is examined to determine whether local stack usage is required. For a routine having tail routine calls only and a requirement of local stack usage, wrapper routine assembly code instructions of a first type are generated. If the routine includes tail calls only and no requirement for local storage, wrapper routine assembly code instructions of a second type are generated. If the routine incorporates one or more calls within the body thereof, the routine is further examined to determine whether a live register is required over any of the calls. If so, wrapper routine assembly code instructions of a third type are generated. If the routine incorporates calls within the body thereof and a live register is not required over any call, wrapper routine assembly code instructions of a fourth type are generated.

Method and system for wrapper routine optimization

System and method for reducing the occurrence of window use overflow

An approach for allocating a set of virtual registers to a set of physical registers using selective spilling is described. A set of code and a spill variable are specified. A code region hierarchy containing a set of code regions is determined based upon the set of code. The first level of the code region hierarchy is evaluated and if the spill variable is referenced in more than one code region, code for performing a spill operation on the specified spill variable is added to the set of code based upon a code region which defines the specified spill variable. In addition, code for performing a reload operation on the specified spill variable is added to the set of code based upon code regions that use the specified spill variable. If the spill variable is only referenced in a single code region in the first level of the code region hierarchy, then code regions that are both in a second level of the code region hierarchy and which correspond to the code region in the first level which references the spill variable are analyzed and code added in a similar manner.

Register allocation via selective spilling

A method and apparatus for allocating registers when compiling code is provided. In response to determining there are insufficient registers associated with a first functional unit of a processor to allocate to a region of code, instructions associated with the region designated for execution on a first functional of processor that may be executed by second functional unit are detected. Those instructions generated for execution on the first functional unit are replaced with the instructions executed on the second functional unit.

Functional unit switching for the allocation of registers

A float register spill cache method for improving the efficiency of usage of floating point single precision registers computer using a microprocessor conforming to the SPARC-V9 architecture specification. Values are temporarily stored in a plurality of double precision registers which are utilized as a float spill cache having a plurality of float spill slots. Values are generally shifted from one of the single precision registers to a second single precision register which is used as a spill pad, and then from the spill pad to a selected one of the float spill slots.

Float register spill cache method, system, and computer program product

Allocation of real registers to virtual or symbolic registers represented by nodes in an interference graph is performed with a compiler using a primary interference graph and a secondary interference graph. The primary interference graph contains the standard edges indicating latency between virtual registers represented by nodes linked by the edges. Secondary links between nodes indicate conditional conflicts which can be tolerated but which, if avoided in the register allocation process, improve the execution speed of program segments. The conditional conflict specifically referenced is the requirement for paired register designation in single precision floating point operations in which registers are identified as pairs, rather than as individual registers.

Method and system for register allocation using multiple interference

Small assembly code routines are inlined with source code prior to optimization processing in a compiler in a data processing system. Each assembly code routine is presented to the compiler in the form of a template having instructions and operands. Whenever a call to the template is detected by the compiler, the instructions and operands of the template are examined by the compiler to determine whether all instructions and operands in the template are recognizable by the compiler for optimization processing. If so, the assembly code template is virtualized by transforming physical registers to virtual registers, and the intermediate code form of the template is combined with the intermediate code form of the source code. This combined code is then subjected to optimization procedures in the compiler, and the result is used to generate the assembly code. The assembly code from any template not eligible for early inlining is later inlined with the assembly code generated by the compiler after the optimization processing.

Method and apparatus for easy insertion of assembler code for

During code generation, a routine is first decomposed into regions. Then, starting from the highest plateau, i.e. the inner most control flow level, the interference graph of each region in a plateau is colored individually. Neighboring regions of the plateau are then combined by connecting the colored nodes of the interference graphs that are live at region boundaries. If connecting the interference graphs render the connected interference graph uncolorable, colored nodes that are live at region boundaries are connected by introducing register to register move or spilling the node. When all neighboring regions of a plateau are combined, the plateau collapses into a region of the lower level plateau. The process is repeated until all plateaus are collapsed and the regions of the base plateau are colored and combined together. Registers are then allocated to the colored nodes.

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Mountain View, CA, United States of America

Kurt J Goebel