Intel Corporation

Fastec International, LLC

Other

Kurt B Robinson

David M Brown

Russell D Eslick

Brian L Dipert

Markus A Levy

Lily C Pao

Steven E Wells

Mickey L Fandrich

Virgil N Kynett

David M Puffer

James Chapple

Brian D Possley

Ray Askew

Dale K Elbert

Thomas E Dever, Ii

Robert N Hasbun

Joseph H Salmon

Owen W Jungroth

Robert E Larsen

Terry L Kendall

David A Leak

Mark J Christopherson

Clark S Thurlo

Gerald S Holzhammer

Jerry A Kreiffels

Kelvin W Lee

Lawrence M Leszczynski

Dhiraj Parmar

Systems and method are disclosed for adaptive and/or autonomous traffic control. In one illustrative implementation, there is provided a method for processing traffic information. Moreover, the method may include receiving data regarding travel of vehicles associated with an intersection, using neural network technology to recognize types and/or states of traffic, and using the neural network technology to process/determine/memorize optimal traffic flow decisions as a function of experience information. Exemplary implementations may also include using the neural network technology to achieve efficient traffic flow via recognition of the optimal traffic flow decisions.

Systems and methods involving features of adaptive and/or autonomous traffic control

A glove comprises a pair of fabric members of the same size and configuration in registration with each other and including opposed ends, with one end narrower than the other end. The fabric members are detachably connected by a two-component connector with one component of the two-component connector being on an inside face of one fabric member and the other component of the two-component connector being on an inside face of the other fabric member. The one fabric member includes a pocket extending along a longitudinal axis of the glove. The pocket is configured to receive a hand of a user and, at the narrower end, includes an entrance for the hand. The pocket comprises a ceiling formed of a first fabric material and a floor of the same first fabric material. The other fabric member has an exterior surface opposite its inner face comprising a cloth material covering an absorbent foam material.

Absorbent glove

A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.

Memory controller hub interface

A flash EEPROM memory device including a plurality of blocks of flash EEPROM memory cells arranged to be accessed in rows and columns, a query memory storing data defining characteristics of the flash memory device that may be used to initialize software device drivers for accessing the device, and an interface for receiving data and commands addressed to the blocks of flash EEPROM memory cells and generating signals for affecting the purpose of the commands in the flash EEPROM memory device, the interface adapted to receive a command scaled to a range of characteristics of a particular flash EEPROM memory device and respond by returning the data stored in the query memory as output depending on characteristics of the particular flash EEPROM memory device.

Interface for flash EEPROM memory arrays

A device level interface for connecting a flash EEPROM memory array to other components of a computer system which interface is designed to provide signals which directly relate to the primitive operations of a flash EEPROM memory array. The interface is adapted to use a fixed command set which allows a query command to be used to determine the functionality of the array. The values returned may be used to initialize software drivers used for accessing the array in primitives which relate to the flash EEPROM memory array.

A flash EEPROM memory device including a memory array having a plurality of blocks of flash EEPROM memory cells arranged to be accessed in rows and columns, a query memory storing data defining characteristics of the flash storage device, and a register interface for receiving data and commands addressed to the blocks of flash EEPROM memory devices and generating signals for affecting the purpose of the commands in the device, the interface including a command register for receiving commands and a plurality of registers for providing the data stored in the query memory as output.

Register interface for flash EEPROM memory arrays

A solid state memory disk that stores data on a sector basis is described. The solid state disk includes an array of FLASH memory devices, which store the sectors of data. Each block of memory within the FLASH array includes data space for storing many sectors of data and a block sector translation table. The block sector translation table identifies each sector of data stored in the block's data space by a sector number. The solid state disk also includes a controller. Among its many responsibilities, the controller manages the writing of sector data into the array and the reading of sectors of data from the array. The controller responds to a write request by seeking an earlier version of the sector which has a logical sector number equal to the sector's sector number and marking that sector dirty. Afterward, the controller allocates free memory space for the sector of data. The sector of data is then written into the allocated memory space. The controller reads sectors of data by seeking a sector header translation table to convert sector numbers into physical addresses.

Sector-based storage device emulator having variable-sized sector

A storage system contains a solid state disk drive having a plurality of memory cells to store the files, including file system control information and data. In a high density mode, the solid state disk drive stores more than one bit per memory cell, and in a reliable mode, the solid state disk drive stores one bit per cell. A file configuration system stores file system control information in the reliable mode and stores data, when specified, in the high density mode. The file configuration system includes a multi-level cell extension unit that generates commands to the memory cells. A data compression unit is provided to compress file data. A block size for the data compression unit is calculated in accordance with the number of bits per cell stored in the high density mode. The file configuration system further includes an error detection and correction (EDC) unit to detect and correct data stored in the high density mode. The storage system may be implemented to operate with the personal computer memory card industry association (PCMCIA) standard.

File system configured to support variable density storage and data

A memory card includes a plurality of memories, each having an array that includes a first block and a second block. Control circuitry is coupled to the array for controlling memory operations of the array. A block write protect circuit is provided for storing block lock data to selectively lock control circuitry from accessing the array for the memory operations. The block write protect circuit locks the control circuit from accessing (1) the first block when the block write protect circuit stores a first datum of the data and (2) the second block when the block write protect circuit stores a second datum of the data. A control input is coupled to the block write protect circuit for applying a control signal to enable the block write protect circuit to lock the control circuitry in accordance with the data. The memory card further includes a register circuit coupled to the control input of each of the plurality of memories for storing a control datum to generate the control signal. When the register circuit stores the control datum to generate the control signal, the block write protect circuit of each of the plurality of memories is enabled to lock the respective control circuitry from selectively accessing the respective first and second blocks in accordance with the respective block lock data.

Memory card with erasure blocks and circuitry for selectively protecting

A method for compressing a set of file structures in a flash memory subsystem is disclosed. During a clean-up operation, a sibling chain of the file structures stored in a logical block of the flash memory subsystem is traversed. If a file structure is followed by deleted file structures in the sibling chain, then the file structure is transferred to a spare logical block and the sibling pointer of the file structure is programmed bypass the deleted file structures. If a deleted file structure in the sibling chain is referenced by a previous file structure in the sibling chain, then the deleted file structure is transferred to the logical block and recycled.

Managing file structures for a flash memory file system in a computer

A non-volatile semiconductor memory that is erased in blocks is described. The non-volatile semiconductor memory includes an active block for storing first data and a reserve block for storing second data. The second data is a copy of the first data. The copy is made during a clean-up operation prior to erasure of the active block. The non-volatile semiconductor memory also includes a mapping table for mapping a logical address of an allocation unit to a physical address of a sector within the non-volatile semiconductor memory.

Growing community of inventors

Newcastle, CA, United States of America

Kurt B Robinson