International Business Machines Corporation

Kurt Alan Tallman

Robert C Wong

Vincent James McGahay

David Goren

Henry Atkinson Nye, Iii

Casey Jon Grant

Rachel Gordin

Karen Lynne Holloway

Youri V Tretiakov

Sue Ellen Strang

Sabastian T Ventrone

A method for determining the layout of an interconnect line is provided including: providing a required width for the interconnect line; determining a layout of the interconnect line including slotting the interconnect line to provide two or more fingers extending along the interconnect line with an elongate slot separating adjacent fingers; and determining a number of elongate apertures to be arranged across the width of the interconnect line by comparing the required width with a maximal width for a solid metal feature, and a minimal elongate aperture width. The two or more fingers and elongate slot may be of constant width and equally spaced across the interconnect line width. The method may include selecting the number of fingers and the width of the slots to optimize the layout for a given layer technology.

Layout determining for wide wire on-chip interconnect lines

Disclosed are embodiments of an improved design method, the results of which are a final design structure for an integrated circuit that incorporates, not only layout information, but also client-specific manufacturing information (e.g., import/export information, service requests, processing directives, purchase order requirements, design rule information, etc.) in the same data format in hierarchical form. Also disclosed are embodiments of a manufacturing control method and system. In these embodiments, a final design structure, such as that described above, is received at tape-in. The information contained therein (particularly, the client-specific manufacturing information) is sorted by type and then forwarded to the appropriate tools within the manufacturing facility for processing. By providing the client-specific manufacturing information directly to each manufacturing facility in the final design structure in conjunction with the layout information, the embodiments eliminate the need for independent information gathering by each manufacturing facility.

Manufacturing control based on a final design structure incorporating both layout and client-specific manufacturing information

Described herein is a method for selectively enlarging vias connecting two different layers of conductors in a semiconductor device. Whether or not an individual via is extended on each of its edges is determined by the distance of the edge to the neighboring features. Since many vias can be selectively enlarged along one or more edges without infringing upon neighboring structures, via integrity and conductive characteristics are improved.

Variable data compensation for vias or contacts

A copper-interconnect, low-K dielectric integrated circuit has reduced corrosion of the interconnect when the crackstop next to the kerf is also used as the primacy barrier to oxygen diffusion through the dielectric, with corresponding elements of the crackstop being constructed simultaneously with the circuit interconnect elements; e.g. horizontal interconnect elements have a corresponding structure in the crackstop and vias between interconnect layers have corresponding structures in the crackstop.

Crackstop and oxygen barrier for low-K dielectric integrated circuits

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Essex Junction, VT, United States of America

Kurt Alan Tallman