International Business Machines Corporation

Hgst Netherlands, B.v.

Hitachi Global Storage Technologies Netherlands B.v.

Western Digital Technologies, Inc.

Kurt A Rubin

Hal Jervis Rosen

Timothy Carl Strand

Margaret E Best

Wayne Isami Imaino

Wade Wai-Chung Tang

Michael Grobis

Terry W McDaniel

Wade W-c Tang

Thomas R Albrecht

Luiz M Franca-Neto

Mario Blaum

Brian Rodrick York

Bruno Jean Marchon

Bernhard E Knigge

John Edward Kulakowski

Ernesto Esteban Marinero

Bruce David Terris

Manfred Ernst Schabes

John S Foster

David Thomas Margulies

Mac D Apodaca

Charles Mathew Mate

Blair I Finkelstein

Dan Saylor Kercher

Andrew A Gaudet

Martin Y Chen

Quang Le

Erhard Theodor Schreck

Jeffrey Scott Lille

Zvonimir Z Bandic

Aron Pentek

Neil Smith

Karl Arnold Belser

James M Zavislan

Yimin Hsu

Dejan Vucinic

Andrew Ching Tam

Peter Michael Baumgart

Patrick Braganca

Thao Anh Nguyen

Daniel Bedau

Ricardo Ruiz

Paul B Comita

Olav Hellwig

Elizabeth Ann Dobisz

Jerry E Hurst, Jr

Xiaoping Bian

Lei Wan

Mason Lamar Williams

Daniel Rugar

Nian Xiang Sun

Derek Stewart

Milton Russell Latta

Qing Zhu

Luis Vitorio Cargnini

Thomas Edward Karis

Glenn T Sincerbox

John C Read

Young-Suk Choi

James Lamar Nix

Grace Lim Gorman

Vijay Prakash Singh Rawat

Richard Longstreth White

Gabriel Zeltzer

Judson A McDowell

Bala Krishna Pathem

Jaquelin K Spong

Kanaiyalal Patel

Franck Rose

Walter Eugene Weresin

Neale Marvin Jones

Franck Dreyfus Rose Dit Rose

Roger W Barton

Vincent Marrello

Yu-Sze Yen

Charles Raymond Davis

Steven Gary Schmid

Hal A Rosen

Tushar Keshubhai Suther

Yenyu Hsieh

Takao Suzuki

Harris Anthony Notarys

Hin Pong Edward Lee

A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory device. A selector, in line with a memory element, may be degraded with repeated temperature excursions as current passes through a stack during the read/write process. The selector changes from an amorphous state to become crystalline thus reducing the life of a memory device. The memory device includes a word line, a bit line disposed perpendicular to the word line, a stack&#x2014;including a memory element, a selector, and a spacer&#x2014;disposed between the word line and bit line, and one or more insulating layers surrounding an outer surface of the stack disposed between the word line and bit line. By surrounding the selector with a high thermal conductive heat-sink material, heat is directed away from the selector helping maintain the selector's amorphous state longer.

Thermal management of selector

Embodiments described herein generally relate to the use of three-dimensional solid state memory structures, both volatile and non-volatile, utilizing a Network-on-Chip routing protocol which provide for the access of memory storage via a router. As such, data may be sent to and/or from memory storage as data packets on the chip. The Network-on-Chip routing protocol may be utilized to interconnect unlimited numbers of three-dimensional memory cell matrices, spread on a die, or multiple dies, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits include a reduction in total density as compared to two-dimensional solid state memory structures utilizing a Network-on-Chip routing protocol, improved signal integrity, larger die areas, improved bandwidths and higher frequencies of operation.

Multilayer 3D memory based on network-on-chip interconnection

Embodiments of the present disclosure generally relate to non-volatile memory and, in particular, non-volatile memory with adjustable cell bit shapes. In one embodiment, an adjustable memory cell is provided. The memory cell generally includes a gate electrode, at least one recording layer and a channel layer. The channel layer generally is capable of supporting a depletion region and is disposed between the gate electrode and the at least one recording layer. In this embodiment, upon activating the gate, the channel layer may be depleted and current initially flowing through the channel may be steered through the at least one recording layer.

Non-volatile memory with adjustable cell bit shape

The present disclosure generally relates to a nano-particle matrix in a 3D NVM RRAM device. The RRAM device utilizes a material that may be deposited into high aspect ratio channels, has good cycle ability, short erase and write times, and write/erase voltages that are compatible with CMOS. The RRAM material is disposed between two electrodes of the device and includes conductive nano-particles that are distributed within an insulating matrix. The particles are distributed below the percolation threshold.

Nano-particle matrix for 3D NVM RRAM

A method and apparatus for controlled switching of a magnetoresistive random access memory device is disclosed herein. The method includes delivering a current to a magnetoresistive random access memory device, wherein the MRAM device is in a first state, measuring a voltage drop across the magnetoresistive random access memory device in real-time with a resistance detector, wherein a voltage drop beyond a threshold voltage equates to switching from a first state to a second state, the first state different from the second state, determining whether the MRAM device has switched from the first state to the second state, and stopping the current delivered to the magnetoresistive random access memory device.

Method for controlled switching of a MRAM device

Embodiments of the present disclosure generally relate to memory devices having enhanced perpendicular magnetic anisotropy. The memory device includes a plurality of first leads, a plurality of second leads, and a plurality of memory cells having a plurality of magnetic layers and a tunneling barrier layer. An interfacial layer is incorporated in each memory cell between one of the magnetic layers and the tunneling barrier layer to enhance perpendicular magnetic anisotropy, while preserving high tunneling magnetoresistance.

Magnetoresistive effect devices having enhanced magnetic anisotropy

The present disclosure relates to a method for fabricating an ion-implanted bit-patterned medium. The method includes providing a medium, the medium having a magnetic layer and a substrate and the magnetic layer includes migrating components. The method further includes forming a patterned mask layer on the surface of the magnetic layer and then ion-implanting the medium through the patterned mask layer, wherein the exposed portions of the magnetic layer comprise trench regions, the covered portions of the magnetic layer comprise island regions, and the transition areas between the trench regions and the island regions comprise boundary regions, wherein the island regions have more favorable magnetic properties than the trench regions. The method also includes annealing the medium, wherein the migrating components diffuse from inside the island regions towards the trench regions.

Annealing treatment for ion-implanted patterned media

A method for polishing a carbon overcoat of a magnetic media that results in a smooth surface free of carbon cluster debris. The method involves forming a magnetic disk having a carbon overcoat formed thereon. The carbon overcoat is then polished in the presence of ozone (O). The heat from the polishing process along with the presence of the ozone, cause any carbon particles removed by the polishing to form COgas so that there is no remaining carbon particle debris on the surface of the disk.

Vapor phase chemical mechanical polishing of magnetic recording disks

The present disclosure relates to a planarized bit-patterned magnetic medium that has a magnetic layer, including island regions and trench regions, a first carbon layer applied over the magnetic layer, and a second carbon layer applied over the first carbon layer, wherein the second carbon layer has been removed in the island regions. The first carbon layer may have a lower material removal rate when exposed to chemical-mechanical polishing than the second carbon layer. The present disclosure also relates to a method for planarizing a bit-patterned magnetic medium and a slurry composition for the chemical-mechanical polishing of carbon layers, the slurry composition including an oxidizer component, a catalyst component, a particulate component, and a reaction control component.

Composition and method for planarized bit-patterned magnetic media

The present disclosure relates to a magnetic medium that includes a substrate and a bit patterned magnetic layer applied to the substrate. The bit-patterned magnetic layer includes islands and each island includes a first magnetic material having a first magnetic anisotropy and that has a top surface, a bottom surface, and a peripheral surface. Each island also includes a second magnetic material covering the peripheral surface of the first magnetic material and having a second magnetic anisotropy that is higher than the first magnetic anisotropy. In one embodiment, the first magnetic material may comprise a nucleation domain in a centrally located surface portion of the magnetic islands and/or the second magnetic material may comprise an outer shell on the peripheral surface of the islands.

Reduced adjacent track errors in bit-patterned media

According to one embodiment, a patterned magnetic storage medium is disclosed herein. The magnetic storage medium includes a magnetic domain, a substantially non-magnetic region laterally adjacent to the magnetic domain, and an exchange spring structure disposed between the magnetic domain and the laterally adjacent non-magnetic region wherein the exchange spring structure comprises implanted ions.

Patterned magnetic storage medium

The disclosure relates generally to a method for fabricating a patterned medium. The method includes providing a substrate with an exterior layer under a lithographically patterned surface layer, the lithographically patterned surface layer comprising a first pattern in a first region and a second pattern in a second region, applying a first masking material over the first region, transferring the second pattern into the exterior layer in the second region, forming self-assembled block copolymer structures over the lithographically patterned surface layer, the self-assembled block copolymer structures aligning with the first pattern in the first region, applying a second masking material over the second region, transferring the polymer block pattern into the exterior layer in the first region, and etching the substrate according to the second pattern transferred to the exterior layer in the second region and the polymer block pattern transferred to the exterior layer in the first region.

Method for separately processing regions on a patterned medium

An apparatus, system, and method are provided for reducing edge damage of a disk during chemical mechanical polishing. The apparatus includes a disk carrier configured to receive a disk, the disk having an outside edge and an inside edge, a raised ring adjacent the outside edge of the disk and extending from a surface of the disk carrier to a height greater than a height of the disk, and a raised column adjacent the inside edge of the disk and having a height greater than a height of the disk. The system includes a disk carrier for receiving a disk, a raised ring adjacent the outside edge of each opening, and plugs insertable into a central opening in the disk and having a height greater than a height of the disk. The method includes providing the apparatus, inserting a disk into the apparatus, and polishing the disk.

Uniformity during planarization of a disk

Growing community of inventors

Santa Clara, CA, United States of America

Kurt A Rubin