Intel Corporation

Hrl Laboratories, LLC

Hughes Electronics Corporation

Kursad Kiziloglu

Daniel P Docter

Shivakumar Seetharaman

Fabrice Paillet

Adele E Schmitz

Thomas P Thomas

Michael W Altmann

Robert J Munoz

Kevin William Glass

Jason Seung-Min Kim

Georgios Asmanis

Charles H Fields

Nitin N Garegrat

Michael C Rifani

Andrew Yang

Cindra Widya Abidin

Nasima Parveen

Jose Robins

Dmitry Sergeyevich Lukiyanchenko

Eric S Shapiro

John Mark Matson

Anitha Loke

Ming Hu

David Y Fang

Embodiments may relate to a substrate for use in a system in package (SIP). The substrate may include a first couple to couple with a first component via a permanent couple such that the first component is communicatively coupled with a bridge. The substrate may further include a second couple to removably couple with an interposer such that the interposer is communicatively coupled with the bridge via a communicative couple. Other embodiments may be described or claimed.

Removable interposer

Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.

Proactive Di/Dt voltage droop mitigation

In accordance with some embodiments, a current-balanced logic circuit includes a first sense amplifier, a second sense amplifier, and a current-source transistor which provides bias current to the first and second sense amplifiers. The first and second sense amplifiers are alternately activated by first and second differential clock signals, and when activated convert data received on differential input lines into logical values for storage in respective storage circuits. The storage circuits may be flip-flops, latches, keeper circuits, or other circuits for storing data.

Current-balanced logic circuit

In one embodiment, the present invention includes a differential traveling wave amplifier having a lumped differential preamplifier stage and a distributed differential amplifier stage coupled by a differential end termination interface. In certain embodiments, the distributed differential amplifier stage may include transverse electromagnetic transmission lines coupled between its input and output.

Differential traveling wave driver amplifier

A method for making a thin film device on integrated circuits including the steps of applying a first photoresist layer to a first surface, and patterning the first photoresist layer to have at least a first opening that exposes the first surface. A film is deposited onto the first photoresist layer, wherein a portion of the deposited film is deposited onto the exposed first surface. A second photoresist layer is applied onto the deposited layer, wherein the second photoresist layer is applied to the portion of the deposited film within the first opening and covers a second portion of the deposited layer, wherein the first photoresist layer and the second photoresist layer assist in the defining of the deposited layer. The deposited layer, first photoresist layer, and second photoresist layer are selectively removed, therein exposing the first surface and the second portion of the deposited layer.

Thin film devices and method for fabricating thin film devices

Disclosed is a method of reducing the conductivity/charge of a layer of group III-V semiconductor doped with Sn. The method includes the steps of: forming an region of SiOon the semiconductor layer; annealing at least the semiconductor layer and the region of SiOat a temperature sufficiently high to cause atoms of the Sn dopant to leach from the semiconductor layer into the region of SiO; and removing the region of SiOafter the annealing step is performed. The method can be used, for example, during the manufacture of HEMT, PHEMT, MESFET and HBT devices.

Method of reducing the conductivity of a semiconductor and devices made thereby

Described is an apparatus comprising a transimpedance amplifier to receive an input current from a photodiode and provide an output voltage at first and second differential output terminals. A receive signal strength indicator may generate a differential receive signal strength indication (RSSI) signal based, at least in part, upon a voltage across the first and second differential output terminals.

Transimpedance amplifier with receive signal strength indicator

Described are a circuit and system to provide an output signal in response to composite input signal comprising an AC signal component and a DC signal component. An amplifier provides an amplified voltage signal in response to a voltage representative of the composite signal. A filter may provide a filtered voltage signal having a magnitude that is representative of a magnitude of the DC signal component in response to the amplified voltage signal. A DC signal removal circuit may substantially remove at least a portion of the DC signal component from an input terminal in response filtered voltage signal.

DC offset cancellation circuit, system and method

Disclosed is a method of reducing the conductivity/charge of a layer of group III-V semiconductor doped with Sn. The method includes the steps of: forming an region of SiO on the semiconductor layer; annealing at least the semiconductor layer and the region of SiO at a temperature sufficiently high to cause atoms of the Sn dopant to leach from the semiconductor layer into the region of SiO ; and removing the region of SiO after the annealing step is performed. The method can be used, for example, during the manufacture of HEMT, PHEMT, MESFET and HBT devices.

A method for stripping photoresist used as an etch mask in carbon based reactive ion etching includes flood exposing a patterned photoresist with a light and cyclically exposing the photoresist with an oxygen plasma in between the carbon based plasma. The step of cyclically exposing occurs after the step of flood exposing. The step of flood exposing includes the step of decomposing photosensitive compounds in the photoresist, while the step of cyclically exposing includes the step of cyclically removing layers of the photoresist.

Growing community of inventors

Los Angeles, CA, United States of America

Kursad Kiziloglu