Texas Instruments Corporation

Kuong Hua Hii

Theo J Powell

Danny R Cline

Wah Kit Loh

Daniel R Cline

James M Garnett

Siak Kian Lee

Tek Yong Lim

Keat Peng Lee

An integrated circuit has a built-in self-test (BIST) arrangement (). The built-in self-test arrangement includes a read only memory (ROM), () that stores test algorithm instructions. A ROM logic circuit () receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST registerreceives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

Built-in self-test arrangement for integrated circuit memory devices

An integrated circuit has a built-in self-test (BIST) arrangement (). The built-in self-test arrangement includes a read only memory (ROM), () that stores test algorithm instructions. A Rom logic circuit () receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST registerreceives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

An integrated circuit has a built-in self-test (BIST) arrangement ( ). The built-in self-test arrangement includes a read only memory (ROM), ( ) that stores test algorithm instructions. A ROM logic circuit ( ) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

A test enable control for a built-in self-test of a memory device is provided. In one embodiment of the present invention, a test enabling system is provided. The test enabling system comprises an enable test circuit (62), a plurality of test algorithms stored in a read only memory (72) and a program counter (66) operable to control the execution of the test algorithm. The first instruction of each test is a jump test enable instruction (130) comprising a jump test instruction and an address in the read only memory (72) corresponding to the next test algorithm. The enable test circuit (62) is operable to signal to the program counter (66) if a particular test algorithm is enabled.

Test enable control for built-in self-test

A short disturb test algorithm for built-in self-test is provided. The short disturb test (108) initially writes a background pattern to all cells in a memory array (24). After verifying the background pattern was written, the opposite of the background pattern is written to a single row of the memory array for a fixed time. After that fixed time has elapsed, the original background pattern is written to the row. The memory array is then refreshed and the next row is written to. After all rows have been written to, the memory array (24) is checked for failures.

Short disturb test algorithm for built-in self-test

A read-only memory (ROM) embedded mask release number for a built-in self-test of a memory device is provided. A synchronous dynamic random access memory (10) comprises a conventional memory (12) and a built-in self-test arrangement (14). The built-in self-test arrangement (14) includes a read only memory (ROM) (72) which stores a plurality of algorithms. Each algorithm is comprised of a series of array access instructions (140) and program access instructions (142). The last instruction in ROM (72) is an idle instruction (120). Associated with idle instruction (120) is an identification number (132). Once stored in ROM (72), the identification number (132) can be read without the use of additional equipment.

ROM embedded mask release number for built-in self-test

A data invert jump instruction test for a built-in self-test of a memory device is provided. The data invert system comprises a read only memory (72) operable to store a plurality of test algorithms wherein at least one of the test algorithms includes a data invert jump instruction (160). Also included is a data invert circuit (178) coupled to the read only memory (72) and a toggle register (188) within the data invert circuit (178). The toggle register (188) is set to one when the data invert jump instruction (160) occurs for the first time in the test algorithm. This causes the data invert circuit (178) to output the inverse of the data inputted through the data invert circuit (178).

Data invert jump instruction test for built-in self-test

An integrated circuit memory device (10) is provided that has a self test monitor mode. The memory device (10) includes a memory array (26) having a plurality of memory cells. The memory device (10) further includes a built-in self test circuit (12) connected to receive a self test select signal. The built-in self test circuit (12) is operable, when the memory device (10) is in self test mode, to generate internal self test signals for operating and testing the memory array (26). A data buffer (28) is connected to receive the internal self test signals and a monitor mode signal. The data buffer (28) is operable, when the memory device (10) is in self test monitor mode, to connect the internal self test signals to terminals of the memory device (10) to provide the internal self test signals externally from the memory device (10). The monitored internal self test signals can be used to verify operation of the built-in self test circuit (12). The monitored self test signals can also be used in a tester mode to test other memory devices.

Integrated circuit memory device having built-in self test circuit with

An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

An internal/external clock option for built in self test is provided. In one embodiment of the present invention, a clock selection circuit (150) is provided. The clock selection circuit (150) comprises an external clock source (152) and an internal clock source (177). A first multiplexer (164) is provided and has the external clock source (152) and the internal clock source (177) as data inputs and an internal clock selection bit value (B.sub.-- CLKMUXB 176) as a data select input. A second multiplexer (156) having the external clock (152) and the output of the first multiplexer as data inputs and a data select input (BCLK.sub.-- EN) based on whether a self-test mode is activated (BIST.sub.-- EN) and the internal clock selection bit value (B.sub.-- CLKMUXB) is also provided. The external clock source (152) or internal clock source (177) is selected based on the value of the internal clock selection bit value (B.sub.-- CLKMUXB 176) and whether the self test mode is activated (BIST.sub.-- EN).

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Kuong Hua Hii