Texas Instruments Corporation

Teradyne, Inc.

Other

Kuok Y Ling

Hisashi Shichijo

Chin-Yu Tsai

Zhiliang Julian Chen

Katsuo Komatsuzaki

William Robert Krenik

Cosmin Iorga

Charles M Branch

Dale J Skelton

Feng Ying

Lieyi Fang

Alan B Hussey

Martin Kulas

Myron G Manternach

Chong In Chi

A differential delay cell is disclosed. The delay cell includes a voltage bus and a differential pair of MOS transistors having respective source terminals coupled to define a current node, and respective drain terminal outputs that cooperate to form a differential output. A current source is disposed at the current node while a differential diode-connected load is disposed between the differential pair and the voltage bus. The differential diode-connected load comprises at least one n-channel MOS transistor configured as a diode.

Low-jitter delay cell

A duty cycle correction circuit for changing the duty cycle for a differential periodic signal is disclosed. The duty cycle correction circuit includes input circuitry for receiving a first differential signal. The differential signal exhibits a first signal component and a complement signal component, each of the components having initial high and low signal levels and respective first and second DC bias levels. The input circuitry includes a differential output having a first path for propagating the first signal component and a second path for propagating the complement signal component. Programmable load circuitry couples to the differential output and includes a programmable input. The load circuitry operates to programmably vary the DC bias level of at least one of the signal components. A differential gain amplifier is coupled to the first differential output and disposed downstream of the load circuitry.

High-speed duty cycle control circuit

A method for the fabrication of a light-sensing diode in a high-resistivity semiconductor substrate. A high-energy implant of ions into the substrate is patterned to form an annular well of the same conductivity type as the substrate; followed by a second high-energy implant of the opposite conductivity type, within the center of the annulus; followed by a third implant, of lower energy and high dosage, to form a region of the first conductivity type extending laterally near the substrate surface. The resulting diode junction is thereby patterned to include two planes near the substrate surface, allowing incident light to traverse the junction twice.

CMOS photodiode having reduced dark current and improved light sensitivity and responsivity

A circuit for providing a symmetrical output signal to a communication system. The circuit includes an input circuit ( and ) for receiving an input signal and a symmetry circuits ( and ) advantageously configured to provide an output signal exhibiting a symmetrical rising and falling edge waveform in response to the received input signal. An integrated power source (I ) provides current to a common node (N ) in which current is advantageously steered to each half circuit ( and ) to reduce voltage variation on the common node during voltage transition of the input signal, hence, reducing current fluctuation from the current source.

Delay circuit with current steering output symmetry and supply voltage insensitivity

A differential D flip-flop is disclosed including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The data set circuit has a first differential input and a first differential output. The first data store circuit couples to the output of the first data set circuit. The cell further includes a differential clock circuit and a differential reset circuit. The clock circuit having complementary clock inputs to alternately set and store data in the data set and data store circuits. The differential reset circuit ties to the differential output and is operative in response to a reset signal to force the differential output to a predetermined logic level. The differential reset circuit includes matched complementary reset drivers to exhibit like capacitances. The slave cell is formed substantially similar to the master cell, and includes a second differential input coupled to the first differential output of the master cell.

High-speed fully balanced differential flip-flop with reset

A light-sensing diode having improved efficiency due to an extended junction geometry that provides more than one level of interaction with the light input.

A light-sensing diode fabricated in a semiconductor substrate having a surface protected by an insulator, comprising a first region of one conductivity type in this substrate, a second region of the opposite conductivity type forming a junction with the first region in the substrate; this junction having a convoluted shape, providing two portions generally parallel to the surface, and a constricted intersection with the surface; and a gate for applying electrical bias across the junction, this gate positioned on the insulator such that it covers all portions of the junction intersection with the surface, thereby creating a gate-controlled photodiode.

Integrated CMOS structure for gate-controlled buried photodiode

A differential D flip-flop is disclosed including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The data set circuit has a first differential input and a first differential output. The first data store circuit couples to the output of the first data set circuit. The cell further includes a differential clock circuit and a first current source for generating a fixed bias current in the master cell. The clock circuit having complementary clock inputs to alternatingly set and store data in the data set and data store circuits. The slave cell is formed substantially similar to the master cell, and includes a second differential input coupled to the first differential output of the master cell. The slave cell further includes a second current source for generating a second bias current in the slave cell, the second current source having programmable inputs for varying the slave cell bias current, thereby controlling the delay characteristic of the flip-flop.

Programmable differential D flip-flop

Integrated structure for reduced leakage and improved fill-factor in CMOS pixel

A decoding scheme for a dual string DAC which reduces the size of the decoding logic while also reducing the number of switches between the two strings of resistors and also eliminating the need for Op-amps between the coarse and fine resistor strings. The present invention provides a decoding circuit to select adjacent pairs of taps 24 of the coarse resistor string 12 using simple decoding blocks 36. In one embodiment of the present invention, a 14 bit decoder is constructed with a course decoding logic of four 3-bit decoders, two levels of switches, an add-one circuit, a multiplexer, and a small amount of overflow logic. An advantage of the present invention is reduced area and power needed to implement the decoding logic for a decoder having only two levels of switches between the coarse and fine resistor strings.

Decoding scheme for a dual resistor string DAC

A switching scheme for driving a three-phase DC motor includes a first end of a first coil 20 coupled to a first end of a second coil 22 and a first end of a third coil 24. A first high side transistor 32 is coupled between a voltage source and a second end of the first coil 20. A second high side transistor 34 is coupled between the voltage source and a second end of the second coil 22. A third high side transistor 36 is coupled between the voltage source and a second end of the third coil 24. A first low side transistor 38 is coupled between the second end of the first coil 20 and a resistor 56. A second low side transistor 40 is coupled between the second end of the second coil 22 and the resistor 56. A third low side transistor 42 is coupled between the second end of the third coil 24 and the resistor 56. An output of a first low side driver 26 is coupled to a gate of the first low side transistor 38. An output of a second low side driver 28 is coupled to a gate of the second low side transistor 40. An output of a third low side driver 30 is coupled to a gate of the third low side transistor 42. A low side reference voltage is coupled to a first input of each of the three low side drivers 26, 28, and 30. The resistor 56 is coupled to a second input of each of the low side drivers 26, 28, and 30. Pre-charge circuitry 64 is coupled to the output of each of the three low side drivers 26, 28, and 30. The pre-charge circuitry 64 provides a pre-charge signal to each of the three low side drivers 26, 28, and 30.

Soft switching scheme for driving three-phase brushless DC motor

A voltage regulation circuit for use in 'H' bridge circuit applications utilizes feedback networks to provide analog voltage regulation of the output nodes during switching of inductive loads. The regulation of the ouptut nodes during switching of inductive loads eliminates substrate current injection.

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Plano, TX, United States of America

Kuok Y Ling