Other

Cadence Design Systems, Inc.

Mentor Graphics Corporation

Kuoching Lin

Henry K Yu

Hui Xu

Lungtien Liu

Karun Sharma

Jeff Taraldson

John Hainsworth

Disclosed is an approach to implement snapping techniques that aid the interactive, assisted, or automatic placement of layout instances or groups of layout instances for generating a legal placement layout while reducing or entirely eliminating any subsequent or separate performance of design rule checking with respect to the relevant design rules, constraints, or requirements governing the legality of the instances or groups of instances placed in the placement layout.

Method, system, and computer program product to implement snapping for an electronic design

Disclosed are techniques for implementing group legal placement on rows and grids for an electronic design. These techniques identify a group comprising a plurality of instances. A proxy is identified from the plurality of instances. The group is placed in a row region based in part or in whole upon a plurality of permissible characteristics for the proxy without considering permissible characteristics of one or more remaining instances in the group. A group legality may be performed to determine whether the group is placed in the row region in a group legal manner.

Method, system, and computer program product for implementing group legal placement on rows and grids for an electronic design

The present embodiments relate to implementing an integrated circuit design where a layout of circuit cells on a semiconductor chip is based on positions of the circuit cells on a schematic. According to some aspects, embodiments relate to a method for identifying a plurality of sub-regions on a semiconductor chip layout where each sub-region has a placement constraint. The method further includes assigning circuit cells to sub-regions based on the constraints. The method also includes clustering the circuit cells into clusters based on their positions on the schematic. Circuit cells from each cluster are placed in one or more of the sub-regions based on the proximity of the centers of the clusters to the centers of the sub-regions.

Layout placement mapping from schematic placement of circuit cells

Techniques are disclosed for clustering circuit paths in an electronic design automation process for use in improving the timing characteristics of the overall circuit design. Circuit paths included in the cluster may be subjected to placing and routing as a group to relocate instances of circuit components included in the clustered circuit paths to thereby improve the overall circuit design timing.

Clustering circuit paths in electronic circuit design

Methods are described herein for using a tree structure representation for searching selected areas of a programmable device layout in order to determine the existing component configuration of a device. The tree structure may be generated by assigning root nodes, branch nodes and leaf nodes to portions of a tree structure. A search algorithm may walk the tree structure representation of the device layout to determine the existing component configuration of the device of a selected portion of the device layout. The tree structure is simplified by each node of a set of sister nodes on the tree representing equally sized sub-area of the device layout. The tree structure is capable of representing units of layout of multiple different sizes and non-uniform layout units that may straddle more than one sub-area.

Representing device layout using tree structure

A method to optimize differential pairs, based on timing constraints, includes recognizing that two separate traces form a differential pair, and combining sections of the differential pair into one or more trunks. Then, a propagation delay is determined over the differential pair. The determined propagation delay is compared to a timing constraint for the differential pair. If the timing constraint is not met, a length of one or more of the trunks is adjusted and the propagation delay is redetermined and compared to the timing constraint. If the timing constraint is still not met, the process is repeated until the timing constraint is met or until the timing constraint cannot be met. If the timing constraint is eventually met, the one or more trunks are used to produce an adjusted differential pair.

Method and apparatus for optimizing differential pairs based on timing constraints

In accordance with the teachings of the present invention, an improved method and apparatus for automatically locating the coordinated starting points of a differential pair is provided. In one embodiment, a profile of obstacles is constructed, wherein the obstacles are proximately situated adjacent to a first and second endpoint of a differential pair. A pair of coordinated starting points are determined, corresponding to the first and second endpoints, using the constructed profile. The coordinated starting points are used for routing the differential pair of traces in a coordinated manner.

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Cupertino, CA, United States of America

Kuoching Lin