Au Optronics Corporation

Kuo-Yu Huang

Hsiang-Lin Lin

Te-Chun Huang

Maw-Song Chen

Liu-Chung Lee

Yu-Wei Liu

Ke-Chih Chang

Ming-Yao Chen

Hui-Fen Lin

Yu-Han Huang

Yu-Cheng Chen

Wen-Ching Tsai

Yi-Sheng Cheng

Ching-Yu Tsai

Jia-Hong Ye

Ruei-Pei Chen

Ching-Huan Lin

Tsan-Chun Wang

Ching-Jung Yang

Ting-Chang Chang

Han-Tu Lin

Wei-Ming Huang

Yen-Heng Huang

Po-Tsun Liu

Yueh-Hung Chung

Yu-Hsin Ting

Chi-Wen Chen

Chao-Chien Chiu

Chun-Hao Tung

Ssu-Hui Lu

Wen-Yi Hsu

Ze-Yu Yen

Yi-Chen Chiang

Ai-Ju Tsai

Jen-Chien Peng

Fu-Chun Tsao

Po-Chao Chang

Wen-Ching Sung

Yi-Ji Tsai

Hsin-Ming Liao

Tzeng-Guang Tsai

Mu-Kai Wang

Zheng-Han Li

En-Yung Lin

A pixel array substrate, including multiple pixel structures, multiple data lines, multiple scan line groups, multiple transfer line groups, multiple connection terminal groups, and multiple bridge line groups, is provided. The multiple data lines are electrically connected to the multiple pixel structures and arranged in a first direction. Each scan line group includes multiple scan lines arranged in a second direction. The multiple scan lines of the multiple scan line groups are electrically connected to the multiple pixel structures. Each transfer line group includes multiple transfer lines arranged in the first direction. The multiple transfer lines of each transfer line group are electrically connected to the multiple scan lines of a corresponding scan line group. The bridge line groups are structurally separated. Each bridge line group is electrically connected to a corresponding transfer line group and a corresponding connection terminal group.

Pixel array substrate

A circuit substrate includes a substrate, an active device, a first signal line, a second signal line, a shielding electrode, a data line, a pixel electrode, and a common electrode. The first signal line is electrically connected to the active device, and includes a main portion and a connection portion connected to the main portion. The main portion extends along a first direction. The second signal line extends along a second direction. The second signal line is electrically connected to the connection portion. The shielding electrode overlaps the connection portion in a normal direction of the substrate. The shielding electrode and the second signal line belong to a same conductive layer. The data line is electrically connected to the active device. The common electrode is electrically connected to the shielding electrode.

Circuit substrate

A photosensitive element and a manufacturing method thereof are provided. The manufacturing method of the photosensitive element includes successively depositing a second conductive layer, a photosensitive material layer, and a first top electrode material layer on a substrate; forming a first patterned photoresist layer on the first top electrode material layer; patterning the first top electrode material layer by using the first patterned photoresist layer as a mask to form a first top electrode; removing the first patterned photoresist layer; patterning the photosensitive material layer by using the first top electrode as a mask to form a photosensitive layer; forming an insulation layer having an opening on the first top electrode; and forming a second top electrode on the insulation layer, and the second top electrode is electrically connected to the first top electrode via the opening.

Photosensitive element having substantially flat interface between electrode and photosensitive layer and manufacturing method thereof

A display panel includes a substrate, at least one first transistor, and at least one second transistor. The substrate includes at least one reflective region and at least one transmissible region. The first transistor is configured on the substrate and located on the corresponding reflective region. Each of the first transistors includes a first active layer. The second transistor is configured on the substrate and located on the corresponding transmissible region. Each of the second transistors includes a second active layer. A material of the first active layer is different from a material of the second active layer.

Display panel

An active device substrate and a manufacturing method thereof are provided. The active device substrate includes a substrate, first and second scan lines, a data line, first and second active devices and first and second pixel electrodes. The first active device includes a first semiconductor channel layer, a first gate, a first source and a first drain. The first gate is electrically connected to the first scan line. The first pixel electrode is electrically connected to the first drain. The second active device includes a second semiconductor channel layer, a second gate and a second drain. The first semiconductor channel layer is connected to a source region of the second semiconductor channel layer. The first semiconductor channel layer and the second semiconductor channel layer belong to same layer. The second gate is electrically connected to the second scan line. The second pixel electrode is electrically connected to the second drain.

Active device substrate and manufacturing method thereof

An opposite substrate including a substrate, first light-shielding patterns, second light-shielding patterns, a planarization layer and support members is provided. The support members are located in primary support regions and secondary support regions of the opposite substrate. The first light-shielding patterns respectively extend along a first direction, and a material of the first light-shielding patterns includes an organic material. The second light-shielding patterns respectively extend along a second direction, and a material of the second light-shielding patterns includes metal. The first light-shielding patterns and the second light-shielding patterns are respectively located at opposite sides of the planarization layer. Alternatively, the first light-shielding patterns and the second light-shielding patterns are located at the same side of the planarization layer, and the planarization layer has openings respectively overlapped with the support members located in the secondary support regions.

Opposite substrate

A pixel array substrate including a substrate, an active device, a planarization layer, a first conductive layer, a first insulation layer and a second conductive layer is provided. The active device is disposed on the substrate. The planarization layer covers the active device and has a first opening. The first conductive layer is disposed on the planarization layer and is electrically connected with a first end of the active device. The first insulation layer is disposed on the first conductive layer. The second conductive layer is disposed on the first insulation layer. The first conductive layer and the second conductive layer cover a side surface of the first opening of the planarization layer.

A pixel structure including an active device, a first protection layer, a first electrode, an isolator, a second protection layer and a second electrode is provided. The active device includes a gate, a source and a drain. The first protection layer covers the active device and has a first opening above the drain. The first electrode is disposed above the first protection layer. The first electrode has a side wall corresponding to the first opening. The isolator covers the side wall of the first electrode. The second protection layer covers the first electrode. The second electrode is disposed on the second protection layer, electrically connected to the drain through the first opening, and electrically isolated from the first electrode by the second protection layer and the isolator.

Pixel structure with isolator and method for fabricating the same

A method for fabricating a display panel includes forming a first patterned conductive layer, a gate insulation layer, a semiconductor channel layer, a first passivation layer, a second patterned conductive layer and a pixel electrode on a first substrate. The first patterned conductive layer includes a gate electrode, and the second patterned conductive layer includes a source electrode, a drain electrode and a data line. The patterns of the gate insulation layer, the first passivation layer and the second patterned conductive layer are defined by an etching process and a lift-off process with the same photomask.

Method for fabricating display panel

A display panel including first and second pixel structures and a light shielding pattern layer is provided. The first pixel structure includes a first pixel electrode including first pixel electrode bars, wherein a first maximum spacing is formed between any two adjacent first pixel electrode bars of the first pixel structure. The second pixel structure includes a second pixel electrode including second pixel electrode bars, wherein a second maximum spacing which is larger than the first maximum spacing is formed between two adjacent second pixel electrode bars of the second pixel structure. The light shielding pattern layer has first and second light shielding portions. The area of the second light shielding portion is larger than the area of the first light shielding portion. The first pixel electrode is close to the second light shielding portion and the second pixel electrode is away from the second light shielding portion.

Display panel having a plurality of pixel electrode bars with different spacing

A pixel structure and a manufacturing method thereof are provided. The pixel structure includes a substrate, a scan line, a data line, a first insulating layer, an active device, a second insulating layer, a common electrode and a first pixel electrode. The data line crossed to the scan line is disposed on the substrate and includes a linear transmitting part and a cross-line transmitting part. The first insulating layer covering the scan line and the linear transmitting part is disposed between the scan line and the cross-line transmitting part. The active device, including a gate, an oxide channel, a source and a drain, is connected to the scan line and the data line. The second insulating layer is disposed on the oxide channel and the linear transmitting part. The common electrode is disposed above the linear transmitting part. The first pixel electrode is connected to the drain.

Manufacturing method of pixel structure with data line, scan line and gate electrode formed on the same layer

A display panel is provided. The display panel has a display area and a peripheral area and includes a plurality of pixels, a plurality of data lines and a plurality of signal traces. The pixels are disposed on the display area and arranged in an array. The data lines extend from the display area to the peripheral area and are respectively electrically connected to a plurality of columns of pixel. The signal traces extend from the display area to the peripheral area and are parallel to the data lines. In addition, the data lines and the signal traces are respectively disposed between two columns of pixels, and the signal traces include a plurality of gate signal traces.

Pixel structure with data line, scan line and gate electrode formed on the same layer and manufacturing method thereof

A display panel, which has a display region and a non-display region, includes an active array substrate and an opposite substrate disposed opposite to the active array substrate. The active array substrate includes a substrate, a pixel array, and a driving circuit. The pixel array and the driving circuit are disposed on the substrate, wherein the pixel array is located in the display region and the driving circuit is located in the non-display region. The driving circuit includes a first transparent electrode layer, a second transparent electrode layer, and a dielectric layer. The dielectric layer is located between the first transparent electrode layer and the second transparent electrode layer, wherein the first transparent electrode layer and the second transparent electrode layer are electrically coupled to each other to form at least one transparent capacitor.

A thin film transistor (TFT) array substrate with few processing steps and simple structure is provided, wherein merely two patterned metal layers are required and a patterned planarization layer is adopted to separate the two patterned metal layers from each other and thereby reduce power loading. In addition, the patterned planarization layer has slots to form height differences so as to separate scan lines from common electrodes to further reduce the power loading.

Thin film transistor array substrate and manufacturing method thereof

Growing community of inventors

Hsinchu County, Taiwan

Kuo-Yu Huang