Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo-Yin Chen

Lee-Chung Lu

Chung-Hsing Wang

Wei-Pin Changchien

Shih-Cheng Chang

Chi Wei Hu

Chia-Lin Cheng

Myron O Shak

Wu-An Kuo

Kevin Hung

Ej Wu

A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module.

System and method for reducing processor power consumption

A method and system for integrally checking a chip layout dataset and a package substrate layout dataset for errors are disclosed. The package substrate layout dataset is converted from a first format into a second format in which the chip layout dataset is provided. The chip layout dataset of the second format is combined with the package substrate layout dataset of the second format into a combined dataset. The combined dataset is then checked for errors or design rule violations.

Method for integrally checking chip and package substrate layouts for errors

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Hsin-Chu, Taiwan

Kuo-Yin Chen