Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo-Wei Lin

Chiou-Shian Peng

Yen-Ming Chen

Fu-Jier Fan

Yang-Tung Fan

Cheng-Yu Chu

Shih-Jane Lin

James Chen

Kenneth Lin

Shih-Ming Chen

Yu-Ying Tsai

Shih-Jang Lin

Alex Fahn

Gilbert Fane

Hsien-Tsung Liu

Ta-Yang Lin

Eugene Chu

Charles Tseng

Fu-Jier Fahn

Hwei-Mei Yu

Hui-Peng Wang

Euegene Chu

Gilbert Fan

Eugene Cheu

Chien-Shian Peng

Chiou Shian Peng

Disclosed herein are intermediate and solder bump structures. In one embodiment, a structure comprises a primary solder column comprising primary solder material and configured to electrically contact a bonding pad on a semiconductor substrate. The structure also comprises at least one secondary solder column comprising secondary solder material in electrical contact with the primary solder column, the at least one secondary column having a height and volume less than a height and volume of the primary solder column. In such structures, the primary solder column is further configured to form a primary solder bump comprising the primary solder material and at least a portion of the secondary solder material through cohesion from the at least one secondary solder column when the intermediate structure undergoes a reflow process.

Solder bump and related intermediate structure having primary and secondary portions and method of manufacturing same

Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon. A transparent encapsulant is deposited to planarize the color filter layer and completes the solid-state color image-forming device without conventional convex microlenses.

Colors only process to reduce package yield loss

It is an object of the present invention to provide a method for solder bump formation using a combination of eutectic and high lead solders. The present invention provides a method for improving a solder bump composition for a flip chip.

Solder bump composition for flip chip

Disclosed herein are a method of manufacturing a solder bump on a semiconductor device, a solder bump structure formed on a substrate, and an intermediate solder bump structure. In one embodiment, the method includes creating a bonding pad over a semiconductor substrate, and placing a mask layer over the substrate and the bonding pad. The method also includes forming an opening in the mask layer having a primary solder mold and at least one secondary solder mold joined with the primary mold, where the opening exposes a portion of the bonding pad. In this embodiment, the method further includes filling the primary solder mold and the at least one secondary solder mold with solder material to form corresponding primary and at least one secondary solder columns in electrical contact with the bonding pad. The method also includes removing the mask layer after the filling of the solder molds with the solder material. The method still further includes reflowing the solder material to form a primary solder bump from the solder material of the primary solder column and at least a portion of the solder material from the at least one secondary solder column through cohesion of the solder material from the at least one secondary solder column to the primary solder column when melted.

IC chip solder bump structure and method of manufacturing same

A new process is provided which is an extension and improvement of present processing for the creation of a solder bump. After the layers of Under Bump Metal and a layer of solder metal have been created in patterned and etched format and overlying the contact pad, following a conventional processing sequence, a layer of polyimide is deposited. The solder flow is performed using the thickness of the deposited layer of polyimide to control the height of the column underneath the reflown solder.

Bumping process to increase bump height and to create a more robust bump structure

A new method and processing sequence is provided for the creation of interconnect bumps. A layer of passivation is deposited over a contact pad and patterned, creating an opening in the layer of passivation that aligns with the contact pad. A layer of UBM metal is deposited over the layer of passivation, the layer of UBM is overlying the contact pad and limited to the immediate surroundings of the contact pad. The central surface of the layer of UBM is selectively electroplated after which a layer of solder or solder alloy is solder printed over the electroplated surface of the layer of UBM. A solder flux or paste is applied over the surface of the solder printed solder compound or solder alloy. Flowing of the solder or solder alloy creates the solder bump of the invention.

Method to form very a fine pitch solder bump using methods of electroplating

A wafer bumping method comprising the following steps of. A wafer having fields is provided. The wafer having at least one wafer identification character formed thereon within one or more of the fields. A dry film resist is formed over the wafer. Portions of the dry film resist are selectively exposed field by field using a mask whereby the mask is shifted over the one or more fields containing the at least one wafer identification character so that the one or more fields containing the at least one wafer identification character is double exposed after the mask shift so that all of the one or more fields containing the at least one wafer identification character is completely exposed. The selectively exposed dry film resist is developed to remove the non-exposed portions of the dry film resist. Solder is plated over the wafer exposed by the removed portions of the dry film resist to form solder bumps within the fields not containing at least one wafer identification character so that the at least one wafer identification character is readable by optical character recognition.

Method to make wafer laser marks visable after bumping process

A method of making electrically conductive bumps of improved height on a semiconductor device. The method includes steps of depositing an under bump metallurgy over a semiconductor device onto a contact pad; depositing and patterning a photoresist layer to provide an opening over the under bump metallurgy; depositing a first electrically conductive material into the opening in the photoresist layer; depositing a second electrically conductive material over the first electrically conductive material; removing the photoresist layer and the excess under bump metallurgy; applying a flux agent to the top surface of the second electrically conductive material; hard baking the semiconductor device to remove any oxide; dipping a portion of the semiconductor device in an electroless plating solution; removing the semiconductor device from the electroless plating solution; and reflowing the electrically conductive materials to provide a bump of improved height on the semiconductor device.

Method of making tall flip chip bumps

A method of forming a bump structure, comprising the following steps. A structure having an exposed first conductive structure is provided. A first photoresist layer is formed over the structure and the exposed first conductive structure. A second capping photoresist layer is formed over the first photoresist layer. The first and second photoresist layers being comprised of different photoresist materials. The first and second photoresist layers are patterned to form an opening through the first and second photoresist layers and over the first conductive structure. The second capping photoresist layer prevents excessive formation of first photoresist layer residue during processing. A second conductive structure is formed within the opening. The first and second patterned photoresist layers are stripped. The second conductive structure is reflowed to form the bump structure.

Dual layer photoresist method for fabricating a mushroom bumping plating structure

A new method to form color image sensor cells without damaging bonding pads in the manufacture of an integrated circuit device is achieved. The method comprises, first, forming cell electrodes and bonding pads on a semiconductor substrate. A passivation layer is formed overlying the cell electrodes but exposing the top surface of the bonding pads. The semiconductor substrate is then dipped in a hydrogen peroxide solution to thereby form a metal oxide layer overlying the bonding pads. A first transparent planarization layer is deposited overlying the passivation layer and the metal oxide layer. A color filter photoresist layer is deposited overlying the first transparent planarization layer. The color filter photoresist layer is patterned to form color filter elements to complete the color image sensor cells in the manufacture of the integrated circuit device. The presence of the metal oxide layer prevents damage to the bonding pads from an alkaline developer.

Method to form a color image sensor cell while protecting the bonding pad structure from damage

A method of forming a bump overlying the copper based contact pad to prevent oxidation of the copper based contact pad. A passivation blanket is deposited over a semiconductor device having a copper based contact pad, the passivation blanket includes a first layer overlying the top surface; a second layer overlying the first layer; a portion of the second layer overlying the copper based contact pad is removed leaving the first layer in place; depositing an under bump metallurgy over the semiconductor device, a portion of the first layer overlying the copper based contact pad is removed so that the copper based contact pad has limited exposure to oxygen; depositing an under bump metallurgy over the semiconductor device; removing excess under bump metallurgy; depositing an electrically conductive material over the under bump metallurgy; reflowing electrically conductive material to form a bump overlying the copper based contact pad.

Method of forming a bump on a copper pad

Within a method for forming a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a patterned conductor layer having a topographic variation at a periphery of the patterned conductor layer. There is then formed over the substrate and passivating the topographic variation at the periphery of the patterned conductor layer a planarizing passivation layer formed of a thermally reflowable material. There is then formed upon the planarizing passivation layer a dimensionally stabilizing layer. Finally, there is then thermally annealed the microelectronic fabrication to form from the planarizing passivation layer a thermally annealed planarizing passivation layer. By employing formed upon the planarizing passivation layer the dimensionally stabilizing layer, there is attenuated within the thermally annealed planarizing passivation layer replication of the topographic variation at the periphery of the patterned conductor layer.

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Hsinchu, Taiwan

Kuo-Wei Lin