Intel Corporation

Micron Technology Incorporated

Stmicroelectronics S.r.l.

Ovonyx Inc.

Kuo-Wei Chang

Jong-Won Sean Lee

Elijah V Karpov

Jinwook Lee

F Daniel Gealy

Andrea Gotti

Michael L McSwiney

Jason S Reid

Davide Colombo

Tyler A Lowrey

Stanford R Ovshinsky

Paolo Fantini

Wim Deweerd

Gianpaolo Spadini

Mac D Apodaca

Semyon D Savransky

Sean Jong Lee

James Reed

Roger Hamamjy

Aleshandre M Diaz

Chong W Lim

Jon-Won S Lee

Wim Y Deweerd

A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.

Electrode materials and interface layers to minimize chalcogenide interface resistance

Embodiments of the present disclosure describe chalcogenide glass compositions and chalcogenide switch devices (CSD.) The compositions generally may include 3% to 15%, silicon, 8% to 16% germanium in, greater than 45% selenium, and 20% to 35% arsenic, by weight. The amount of silicon and germanium in a composition generally may include more than 10% by weight. CSDs may include various compositions of chalcogenide glass, and a plurality of them may be used in a memory device, such as die with a memory component, and may be used in various electronic components and systems. Other embodiments may be described and/or claimed.

Chalcogenide glass composition and chalcogenide switch devices

Erosion of chalcogenides in phase change memories using ovonic threshold switch selectors can be reduced by controlling columnar morphology in electrodes used in the ovonic threshold switch. The columnar morphology may cause cracks to occur which allow etchants used to etch the ovonic threshold switch to sneak through the ovonic threshold switch and to attack chalcogenides, either in the switch or in the memory element. In one embodiment, the electrode may be split into two metal nitride layers separated by an intervening metal layer.

Phase change memory including ovonic threshold switch with layered electrode and methods for forming the same

A memory may include two electrodes and phase change material having an amorphous reset state and a partially crystalized set state, coupled between the two electrodes. The phase change material in the set state may have a highly nonlinear current-voltage response in a subthreshold voltage region. The phase change material may be an alloy of indium, antimony, and tellurium.

Low power phase change memory cell

Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times, in some embodiments. In one embodiment, two separate bubblers may be utilized to feed the two organometallic compounds in gaseous form to the deposition chamber so that the relative proportions of the precursors can be readily controlled.

Depositing titanium silicon nitride films for forming phase change memories

Phase change memory including ovonic threshold switch with layered electrode and methods for forming same

A chalcogenide alloy that optimizes operating parameters of an ovonic threshold switch includes an atomic percentage of arsenic in the range of 9 to 39, an atomic percentage of germanium in the range of 10 and 40, an atomic percentage of silicon in the range of 5 and 18, an atomic percentage of nitrogen in the range of 0 and 10, and an alloy of sulfur, selenium, and tellurium. A ratio of sulfur to selenium in the range of 0.25 and 4, and a ration of sulfur to tellurium in the alloy of sulfur, selenium, and tellurium is in the range of 0.11 and 1.

Ovonic threshold switch film composition for TSLAGS material

By making an ovonic threshold switch using a carbon interfacial layer having a thickness of less than or equal to ten percent of the thickness of the associated electrode, cycle endurance may be improved. In some embodiments, a glue layer may be used between the carbon and the chalcogenide of the ovonic threshold switch. The glue layer may be effective to improve adherence between carbon and chalcogenide.

Forming a carbon passivated ovonic threshold switch

A phase change memory including an ovonic threshold switch is formed using a pulsed direct current (DC) deposition chamber using pulsed DC. Pulsed DC is used to deposit a chalcogenide film. Pulsed DC may be also used to deposit a carbon film.

Method of forming phase change memory devices in a pulsed DC deposition chamber

Briefly, in accordance with one embodiment of the invention, a device, such as a memory cell, includes a dielectric layer and a layer of phase-change material with an adhesion layer between the dielectric layer and the layer of phase-change material.

Adhesion layer for a polymer memory device and method therefor

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Cupertino, CA, United States of America

Kuo-Wei Chang