Mosel Vitelic Corporation

Other

United Integrated Circuits Corp.

United Microelectronics Corp.

Kuo-Tung Sung

Huoy-Jong Wu

Ray C Lee

Wen-Ting Chu

Tsong-Minn Hsieh

Liang-Chen Lin

Chih-hsun Chu

Thomas Chang

Shih-Chi Lai

Wen-Doe Su

Mao Song Tseng

A J Chang

Kun-Yu Sung

Yuru Chu

A method and resulting integrated circuit device ( ) such as a flash memory device and resulting cell. The method includes a step of providing a substrate ( ), which has an active region overlying a thin layer of dielectric material ( ). The method uses a step of forming a floating gate layer ( ) overlying the thin layer of dielectric material ( ), which is commonly termed a &ldquo;tunnel oxide&rdquo; layer, but is not limited to such a layer or material. The floating gate layer ( ) has novel geometric features including slant edges ( ), which extend to the dielectric material ( ). The slant edges ( ) create a smaller geometric area for the tunnel oxide region relative to the area between the floating gate layer and the control gate layer.

Method and device for producing undercut gate for flash memory

A dual-gate cell structure with self-aligned gates. A polysilicon spacer forms a second gate ( ) separated from a first gate ( ), which is also polysilicon, by a dielectric layer ( ). A drain region ( ) and a source region ( ) are formed next to the gates within a shallower well. The shallower well is positioned above a deep well region. In one embodiment, the second gate ( ) acts as a floating gate in a flash cell. The floating gate may be programmed and erased by the application of appropriate voltage levels to the first gate ( ), source ( ), and/or drain ( ). The self-aligned nature of the second gate ( ) to the first gate ( ) allows a very small dual-gate cell to be formed.

Poly spacer split gate cell with extremely small cell size

A split gate EPROM cell and a method that includes a gate structure having a sidewall spacer of differential composition disposed about a floating gate which facilitates control of the spacer thickness during fabrication. Controlling the thickness of the spacer allows avoiding a reduction of the distance between the floating gate and the control gate as well as leakage of the charge from the floating gate.

EPROM cell having a gate structure with dual side-wall spacers of differential composition

An EPROM cell and a method that includes a gate structure having a sidewall spacer. The sidewall spacer is made by way of an amorphous or polycrystalline silicon layer, which is converted into an insulating layer such as silicon dioxide. Deposition of the amorphous or polycrystalline silicon layer is more accurate and produces a more uniform layer than conventional dielectric layer deposition.

Flash memory process using polysilicon spacers

A method for improving an edge recess of a shallow trench isolation (STI). A SiO layer with gap-filling ability is formed to fill the edge recess at the top corner of the STI. A part of the SiO layer on the substrate is then removed, leaving a part of the SiO layer to fill the edge recess and to cover a sidewall of the substrate at the edge.

Method of improving edge recess problem of shallow trench isolation

An E,PROM or a flash memory cell having a sharp tip or thin wedge at one of its gates, e.g., the floating gate, for the erasure of electrical charges stored in the floating gate. A recess is formed between a first polysilicon gate and the substrate by removing portions of an insulating layer interposed between the first gate and the substrate. Another insulating layer, e.g., thermal oxide, is formed on the exposed portions of the first gate and the substrate, and partially fills the recess. A second polysilicon layer is formed on the thermal oxide and patterned to form a floating gate. The partially filled recess causes a sharp polysilicon tip or thin wedge to be formed as part of the floating gate. This sharp tip or thin wedge can generate a high electrical field that facilitates the removal of the stored electrical charges from the floating gate.

Memory cell with built in erasure feature

A capped slit provides isolation between adjacent devices of an integrated circuit. The cap and slit provide very high immunity to punchthrough and protect the edge of the slit against becoming exposed during subsequent processing that could otherwise remove field oxide. In one embodiment, the capped slit isolates two cells of a flash EEPROM device, and the field oxide lines the slit and serves as the tunneling oxide in the cells. In another embodiment, the slit is filled with a plug of dielectric material.

Covered slit isolation between integrated circuit devices

The present invention provides a novel integrated circuit device, which has a flash memory cell. The flash memory cell (,) has a tunnel dielectric layer (,) overlying a surface of a semiconductor substrate. A floating gate layer (,) is defined overlying the tunnel dielectric layer. The gate layer has an edge defined thereon, where a sidewall spacer (,) extends along and on the edge. The sidewall spacer includes a first portion defined adjacent to the edge and a second portion extending from the first portion to a region substantially outside the edge. The combination of the sidewall spacer and the gate layer provide a novel surface for increasing gate coupling ratio.

Floating gate method and device

The present invention provides an EPROM and a method for forming the same having increased density. The invention does so by reducing the area required for formation of a contact. Specifically, a storage cell for an electrically programmable read-only memory having a pair of spaced-apart gate structures, with a double wall spacer structure disposed on opposite sides of each gate structure.

High density programmable read-only memory employing double-wall spacers

A dual-gate cell structure with self-aligned gates. A polysilicon spacer forms a second gate (,) separated from a first gate (,), which is also polysilicon, by a dielectric layer (,). A drain region (,) and a source region (,) are formed next to the gates within a shallower well. The shallower well is positioned above a deep well region. In one embodiment, the second gate (,) acts as a floating gate in a flash cell. The floating gate may be programmed and erased by the application of appropriate voltage levels to the first gate (,), source (,), and/or drain (,). The self-aligned nature of the second gate (,) to the first gate (,) allows a very small dual-gate cell to be formed.

A method for fabricating in a non-volatile memory is provided. The method includes providing a substrate having a memory region. A stacked gate structure is formed on the substrate at the memory region. A source region is formed abutting the stacked gate structure, and an isolation structure is formed to isolate the source region, in which a drain region is also formed abutting the stacked gate structure on the opposite side but not actually related to the invention. A first spacer is formed on each sidewall of the stacked gate structure. A conductive layer is form over the substrate and is patterned to remove a portion of a conductive layer. A remaining portion of the conductive layer covers the isolation structure and the source region so as to form a source line, which has an electrical coupling to each source region belong to a same word line. The stacked gate structure is therefore exposed.

Method for fabricating a nonvolatile memory including implanting the source region, forming the first spacers, implanting the drain regions, forming the second spacers, and forming a source line on the source and second spacers

Methods to improve cell performance in ROM semiconductor integrated circuit devices, in particular split gate cell flash EEPROM devices, without the need for increasing cell size or for decreasing tunnel oxide thickness. The threshold voltage under a first gate electrode (,) is adjusted using a first impurity introducing step, such as an ion implant, and the threshold voltage under a split gate electrode (,) is also adjusted using a second impurity introducing step, such as an ion implant. Depending on the type of cell used, the first gate electrode or the split gate electrode may be used as a floating gate electrode and the threshold voltage under the floating gate electrode may be adjusted separately from the other gate electrode to provide improved cell erase performance, with or without increasing the cell size or decreasing the tunnel oxide thickness.

Method to improve cell performance in split gate flash EEPROM

A dual-gate cell structure with self-aligned gates. A polysilicon spacer forms a second gate (213) separated from a first gate (201), which is also polysilicon, by a dielectric layer (207). A drain region (219) and a source region (221) are formed next to the gates. In one embodiment, the second gate (213) acts as a floating gate in a flash cell. The floating gate may be programmed and erased by the application of appropriate voltage levels to the first gate (201), source (221), and/or drain (219). The self-aligned nature of the second gate (213) to the first gate (201) allows a very small dual-gate cell to be formed.

Split gate flash cell with extremely small cell size

Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer (,) that is thin in some regions, such as the cell region, and thicker in other regions (,), such as the periphery region. The method provides the gate oxide layer with different thicknesses without the thickness control problems of prior art methods that use contaminant-containing photoresist with an etching step. According to the present invention, the gate oxide has a first thickness that is sufficiently thin to provide high driving capability for the semiconductor device, and a second thickness that is sufficiently thick to provide high voltage reliability of the semiconductor device.

Method of implementing differential gate oxide thickness for flash EEPROM

A semiconductor device structure with differential field oxide thicknesses. A single field oxidation step produces a nitrided field oxide region (,) that is thinner than a non-nitrided field oxide region (,). The bird's beak (,) of the nitrided field oxide (,) encroaches less into the active cell region than the bird's beak (,) of the thicker non-nitrided field oxide (,). The differential field oxide thicknesses allow isolation of multi-voltage integrated circuit devices, such as flash memory devices, while increasing available active cell area for a given design rule.

Growing community of inventors

Hsinchu, Taiwan

Kuo-Tung Sung