Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo-Sheng Chuang

You-Hua Chou

Chin-Hsiang Lin

Chi-Ming Yang

Chih-Wei Huang

Yusuke Oniki

Ming-Chi Huang

Cheng-Chung Chien

Ming-Hsi Yeh

Nai-Han Cheng

Wen-Yu Ku

Ying-Hsueh Chang Chien

Weibo Yu

Chia-Hsiang Chen

Han-Liang Tseng

Long-Sheng Yeou

Jyh-Shiou Hsu

Chia-Chun Cheng

Ji-Chung Huang

Chien-Fong Chen

Yii-Cheng Lin

Albert Po Chia Chen

Siu-Han Liao

Jun-Ker Yeh

Chi-Fu Chang

A substrate handling device includes a substrate reception area defined by an edge. The substrate reception area includes a planar surface, wherein the edge extends upward from the planar surface. The substrate reception area further includes a plurality of contact structures extending upwards from the planar surface, wherein a first contact structure of the plurality of contact structures directly contacts a side surface of the edge, and a second contact structure of the plurality of contact structures is separated from the edge. The substrate reception area and the planar surface include a first material. At least one contact structure of the plurality of contact structures includes a second material different from the first material, and the second material has a hardness aligned to a hardness of a substrate material.

Substrate handling device and processing chamber

A semiconductor integrated circuit (IC) including a first fin structure having a first aqueous soluble channel layer. The semiconductor IC includes a first gate structure over the first aqueous soluble channel layer, wherein the first gate structure includes a first oxide film directly contacting the first aqueous soluble channel layer, and the first oxide film includes a first material. The semiconductor IC includes a first spacer along the first gate structure, wherein a bottom surface of the first spacer is above an interface between the first oxide layer and the first aqueous soluble channel layer. The semiconductor IC includes a second fin structure having a second aqueous soluble channel layer. The semiconductor IC includes a second gate structure over the second aqueous channel layer, wherein the second gate structure includes a second oxide film directly contacting the second aqueous soluble channel layer, the second oxide film includes a second material.

Semiconductor integrated circuit

A method of forming a conductive powder includes reducing, by a reduction reaction, a conductive powder precursor gas using a plasma to form the conductive powder. The method further includes filtering the conductive powder based on particle size. The method further includes dispersing a portion of the conductive powder having a particle size below a threshold value in a fluid.

Conductive powder formation method and device for forming conductive powder

A substrate handling device includes a substrate reception area defined by an edge. The substrate reception area includes a planar surface, wherein the edge extends upward from the planar surface. The substrate reception area further includes a plurality of contact structures extending upwards from the planar surface, wherein a first contact structure of the plurality of contact structures directly contacts a side surface of the edge, a second contact structure of the plurality of contact structures separated from the edge, a shape of the first contact structure is different from a shape of the second contact structure. The substrate reception area and the planar surface include a first material. Each contact structure of the plurality of contact structures includes a second material different from the first material, and the second material has a hardness aligned to a hardness of a substrate material.

A method for forming a semiconductor structure is provided. The method includes depositing a hard mask layer over a substrate. The method further includes depositing a silver precursor layer over the hard mask layer. The method further includes exposing portions of the silver precursor layer to a radiation, the radiation causing a reduction of silver ions in the irradiated portions of the silver precursor layer. The method further includes removing non-irradiated portions of the silver precursor layer, resulting in a plurality of silver seed structures.

Silver patterning and interconnect processes

A gamma ray generator includes a rotational shaft, a plurality of holders and a plurality of gamma ray sources. The holders are connected to the rotational shaft. The gamma ray sources are disposed in the holders respectively, wherein the holders respectively have an upper portion and a lower portion connecting to the upper portion, and the gamma ray source is placed at an interface between the upper portion and the lower portion.

Gamma ray generator and method of generating gamma ray

A gamma ray generator includes a plate, a plurality of holes and a plurality of gamma ray sources. The plate is configured to rotate along a rotational axis. The holes are disposed in the plate, and the holes are arranged in a matrix. The gamma ray sources are respectively placed in the holes.

Gamma ray generator and gamma ray lithography system

A method of aligning a substrate contact material to a substrate material includes determining a hardness of a substrate material. The method further includes matching a hardness of a substrate contact material to the hardness of the substrate material. The method further includes adding the substrate contact material to a plurality of contact structures of a substrate handling device, wherein the substrate handling device comprises an edge and a planar surface, a first contact structure of the plurality of contact structures extends from the edge, and a second contact structure of the plurality of contact structures extends from the planar surface.

Method of handling a substrate

A method of patterning a material layer includes the following steps. A first material layer is formed over a substrate, and the first material layer includes a first metal compound. Through a first photomask, portions of the first material layer is exposed with a gamma ray, wherein a first metal ion of the first metal compound in the portions of the first material layer is chemically reduced to a first metal grain. Other portions of the first material layer are removed to form a plurality of first hard mask patterns including the first metal grain.

Method of patterning material layer

A photomask includes a patterned photomask plate and a supporting member. The patterned photomask plate has a pattern region and a peripheral region surrounding the pattern region. The patterned photomask plate includes a plurality of openings in the pattern region. The supporting member directly abuts the patterned photomask plate and is in a peripheral region of the patterned photomask plate. The supporting member is formed from a different material than the patterned photomask plate.

Photomask

A device includes a non-insulator structure, a first dielectric layer, and a first conductive feature. The first dielectric layer is over the non-insulator structure. The first conductive feature is in the first dielectric layer and includes carbon nano-tubes. The first catalyst layer is between the first conductive feature and the non-insulator structure. A top of the first catalyst layer is lower than a top of the first conductive feature.

Semiconductor device and method for manufacturing the same

A transistor includes a silicon germanium layer, a gate stack, and source and drain features. The silicon germanium layer has a channel region. The silicon germanium layer has a first silicon-to-germanium ratio. The gate stack is disposed over the channel region of the silicon germanium layer and includes a silicon germanium oxide layer over and in contact with the channel region of the silicon germanium layer, a high-&#x3ba; dielectric layer over the silicon germanium oxide layer, and a gate electrode over the high-&#x3ba; dielectric layer. The silicon germanium oxide layer has a second silicon-to-germanium ratio, and the second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio.

Semiconductor device having interfacial layer and high &#x3ba; dielectric layer

A method including forming a first insulating film over a first fin structure. The method further includes removing the first insulating film to expose a portion of the first fin structure. The method further includes forming a first oxide film over the exposed portion of the first fin structure using a non-aqueous solvent-based chemical.

One of gamma ray lithography systems includes a gamma ray generator and a wafer stage. The gamma ray generator is configured to generate a substantially uniform gamma ray. The gamma ray generator includes a plurality of gamma ray sources and a rotational carrier. The rotational carrier is configured to hold the gamma ray sources and rotate along a rotational axis. The wafer stage is disposed below the gamma ray generator and configured to secure a wafer.

Gamma ray generator, gamma ray lithography system and method of performing gamma ray lithography

A method for wafer pod handling includes at least the following steps. A wafer pod is moved into a load chamber by conveying the wafer pod to the load chamber via one side of a track and removing a cover of the load chamber via an opposing side of the track. The wafer pod that is inside the load chamber is coupled to a port of a platform that is linked to the load chamber. A wafer to be processed is moved from the wafer pod and out of the load chamber to the platform for performing a semiconductor process. Other methods for wafer pod handling are also provided.

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Hsinchu, Taiwan

Kuo-Sheng Chuang