Via Technologies, Inc.

Leltek Inc.

Kuo-Ping Liu

Jiin Lai

Sheng-Chang Peng

Heng-Chen Ho

Chi Hao Chang

You-Ming Chiu

Jyh-Fong Lin

Hsin-Chieh Lin

Yu-Wei Lin

Kuang-Kai Kuo

Chung-Pang Yu

Ying-Yi Liu

Biyun Yeh

A method for transceiving signals and a transceiver using the same are provided. The method includes: configuring a transmitting circuit to transmit a transmitting signal via a first transmitting channel of the transmitting circuit during a transmitting period of the transmitting signal; configuring a switch module to connect the first transmitting channel to a first transducer element of a probe during the transmitting period; and configuring the switch module to disconnect the first transmitting channel form the first transducer element and to connect the first transmitting channel to a second transducer element of the probe during the transmitting period.

Method for transceiving signals and transceiver using the same

An ultrasound apparatus and a method of emitting plane wave are provided. The ultrasound apparatus includes an ultrasound probe, a transceiver circuit, a switch module and a processor. The ultrasound probe has a 1to a Mtransducer elements for respectively emitting ultrasound beams to form the plane wave, and the transceiver circuit has a 1to a Ntransceiving channels. M, N are positive integers, and M is a multiple of N. During a scanning period, the processor controls the switch module to initially and respectively connect the 1-Ntransceiving channels to the 1-Ntransducer elements, such that the 1-Ntransducer elements successively emit the ultrasound beams. After the ultrasound beam is emitted by the Ntransducer element, the processor controls the switch module to respectively connect the 1-Ntransceiving channels to the (N+1)-(2N)transducer elements, such that the (N+1)-(2N)transducer elements successively emit the ultrasound beams.

Ultrasound apparatus and ultrasound emission method

A control chip and operating method for accelerating memory access that can be applied to a memory system whose memory read command actual address is read from a system bus in a number of synchronous transmissions. On receiving a first section read address, the control chip operates to compare the first section read address with an identical bit portion of the write address of the memory-write commands inside a memory-write command queue. If the comparison indicates some difference, permission for executing the memory read command is granted. If the comparison indicates the presence of identical bits, a second section read address is received and compared with an identical bit portion of the write address of the memory-write commands inside a memory-write command queue. If the comparison indicates some difference, permission for executing the memory read command is granted. If the comparison indicates the presence of identical bits, permission for executing the memory read command is granted only after the memory-write command inside the memory-write command queue having an identical write address is executed.

Control chip and method for accelerating memory access

This specification discloses a programmable drive circuit for the I/O port. Using a logic circuit, the driver on the IC I/O port can be programmed to be an open-drained driver or a push-pull driver. In an embodiment of the invention, the programmable drive circuit contains a first transistor group and a second transistor group connected in series between a work voltage and a ground level. A first logic circuit controls the first transistor group, and a second logic circuit controls the second transistor group. The logic circuits are controlled by a select signal so that the first transistor group and the second transistor group become the open-drained driver or the push-pull driver.

Programmable drive circuit for I/O port

A clock generating apparatus and method for generating clock signals of different frequency. The clock generating apparatus and method receives and divides a main clock signal to obtain a reference clock signal. Then, the reference clock signal and the first feedback clock signal are phase-locked to obtain the first clock signal. Moreover, the reference clock signal and the second feedback clock signal are phase-locked to obtain the second clock signal. The reset signal and the first clock signal are received by a divider. The divider then outputs the first feedback clock signal. Another divider receives the reset signal and the second clock signal and then outputs the second feedback clock signal.

Clock generating apparatus and method thereof

A signal delay device having an internal delay lock loop for calibrating the delay interval. The signal delay device receives an input signal and then outputs the signal after a pre-defined delay period. The input signal varies according to a reference clock signal, and the required delay period is a quarter cycle of the clock signal. The delay device includes a multiplexer, an inverter, a phase detector, a counter and a delay element. During calibration, the phase detector, the counter and the delay element form a delay lock loop that can set up the delay time automatically.

Delay device having a delay lock loop and method of calibration thereof

A chip testing system using an internal signal of the chip under test to produce a blanking signal so as to avoid a conflict in the turn-around cycle between input mode and output mode. The preceding signal, posterior signal and reverse phase signal of the output enable signal of the chip under test are used to match with a testing circuit for producing a blanking signal, which is driven only when the output enable signal is at a high potential, enabling the state machine in the chip to control data reading time, so as to avoid a conflict in the turn-around cycle between input mode and output mode.

Chip testing system

A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other clock rate. The first and second clock rates are in virtual synchronism and have a fixed ratio between them. The computer chip set utilizes a phase signal generator capable of generating a set of phase signals and a signal conversion logic circuit for generating the output signal referencing one of the first and second clock rates other than the one referenced by the input signal. This computer chip set can allow the computer mother board to be operated without waiting a state so that the data processing efficiency of the computer mother board can be enhanced. A multiplexer means used in the computer chip set of the invention has an output which is selectively multiplexed between the first clock rate and the second clock rate to serve as a third clock signal. This computer chip set allows the designer to use a slower clock rate to drive the DRAM.

Computer chip set for computer mother board referencing various clock rates

A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other clock rate. The first and second clock rates are in virtual synchronism and have a fixed ratio between them. The computer chip set utilizes a phase signal generator capable of generating a set of phase signals and a signal conversion logic circuit for generating the output signal referencing one of the first and second clock rates other than the one referenced by the input signal. This computer chip set can allow the computer mother board to be operated without waiting a state so that the data processing efficiency of the computer mother board can be enhanced. A multiplexer means used in the computer chip set of the invention has an output which is selectively muliplexed between the first clock rate and the second clock rate to serve as a third clock signal. This computer chip set allows the designer to use a slower clock rate to drive the DRAM.

Growing community of inventors

Taipei, Taiwan

Kuo-Ping Liu