Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Parabellum Strategic Opportunities Fund LLC

Kuo-Ming Wu

Cheng-Yuan Tsai

Cheng-Hsien Chou

Yi-Chun Lin

Sheng-Chau Chen

Yung-Lung Lin

Yi-Min Chen

Yi-Cheng Chiu

Hung-Chou Lin

Hong-Shyang Wu

Wen-Chih Chiang

Shiuan-Jeng Lin

Karthick Murukesan

Sheng-Chan Li

Hau-Yi Hsiao

Jia-Rui Lee

Chun Lin Tsai

Alexander Kalnitsky

Chih-Hui Huang

Kuan-Liang Liu

Wan-Hua Huang

Po-Yu Chen

Chiu-Hua Chung

Ming-Che Lee

Jing-Ying Chen

Dun-Nian Yaung

Jen-Cheng Liu

Yeur-Luen Tu

Ruey-Hsin Liu

Min-Feng Kao

Ching-Chun Wang

Wen-De Wang

Hsing-Chih Lin

Kai-Wen Cheng

Shih-Han Huang

I-Nan Chen

Zhi-Yang Wang

Chia-Shiung Tsai

Ru-Yi Su

Po-Chih Chen

Shih-Pei Chou

Mao-Ching Chiu

Chun-Lin Tsai

Ker-Hsiao Huo

Chih-Yuan Chan

Chen-Chien Chang

Jui-Hsi Cheng

Tian Sheng Lin

Chi-San Wei

Hong-Yang Chen

Jian-Hsing Lee

Hsiao-Chin Tuan

Pao-Tung Chen

Alex Kalnitsky

Chen-Bau Wu

Chi-Chih Chen

Ping-Tzu Chen

Shih-Chung Yin

Shiang-Yu Chen

Wei Tsung Huang

Tien Sheng Lin

Jiann-Tyng Tzeng

Chih-Ming Chen

Chung-Yi Yu

Pei-Kai Liao

Shun-Liang Hsu

Hung-Ling Shih

Chih-Yu Lai

Chung-Jen Huang

Hung-Wen Hsu

Kuo-Hwa Tzeng

Sin-Yao Huang

Yu-Hao Chang

Hung-Kun Chen

Chun-Chi Chen

Guanyu Luo

Chun Liang Chen

Ming Xiang Li

Ming-Jhe Lee

Reuy-Hsin Liu

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.

Semiconductor structure and associated fabricating method

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes bonding a first semiconductor wafer to a second semiconductor wafer. A bond interface is disposed between the first and second semiconductor wafers. The first semiconductor wafer has a peripheral region laterally surrounding a central region. A support structure is formed between a first outer edge of the first semiconductor wafer and a second outer edge of the second semiconductor wafer. The support structure is disposed within the peripheral region. A thinning process is performed on the second semiconductor wafer.

Support structure to reinforce stacked semiconductor wafers

A device and methods of forming the same are described. The device includes a substrate and a first bipolar junction transistor (BJT) disposed over the substrate. The first BJT includes a first base region, a first emitter region, and a first collector region. The device further includes a second BJT disposed over the substrate adjacent the first BJT, and the second BJT includes a second base region, a second emitter region, and a second collector region. The device further includes an interconnect structure disposed over the first and second BJTs, and the interconnect structure includes a first conductive line electrically connected to the first emitter region and the second base region and a second conductive line electrically connected to the first collector region and the second collector region.

Cascaded bipolar junction transistor and methods of forming the same

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a stilted pad structure. A wire underlies a semiconductor substrate on a frontside of the semiconductor substrate. Further, a trench isolation structure extends into the frontside of the semiconductor substrate. The stilted pad structure is inset into a backside of the semiconductor substrate that is opposite the frontside. The stilted pad structure comprises a pad body and a pad protrusion. The pad protrusion underlies the pad body and protrudes from the pad body, through a portion of the semiconductor substrate and the trench isolation structure, towards the wire. The pad body overlies the portion of the semiconductor substrate and is separated from the trench isolation structure by the portion of the semiconductor substrate.

Stilted pad structure

A gate-all-around (GAA) high voltage transistor of the laterally double-diffused metal-oxide semiconductor (LDMOS) type has a loop-shaped gate electrode disposed below a surface of a semiconductor substrate. The loop-shaped gate electrode surrounds a vertical channel formed by a first source/drain region, a body region, and a diffusion region. The first source/drain region is on top, the body region is in the middle, and the diffusion region is underneath. A loop-shaped shallow trench isolation (STI) region surrounds the loop-shaped gate electrode. The diffusion region begins inside the loop-shaped gate electrode, extends under the loop-shaped gate electrode and the loop-shaped STI region, and rises outside the loop-shaped STI region to join with a second source/drain region. This structure allows pitch to be reduced by 40% or linear drive current to be doubled in comparison to an asymmetric NMOS transistor providing otherwise equivalent functionality.

GAA LDMOS structure for HV operation

In an embodiment, a device includes: a gallium nitride device on a substrate, the gallium nitride device including an electrode; a dielectric layer on and around the gallium nitride device; an isolation layer on the dielectric layer; a semiconductor layer on the isolation layer, the semiconductor layer including a silicon device; a through via extending through the semiconductor layer, the isolation layer, and the dielectric layer, the through via electrically and physically coupled to the electrode of the gallium nitride device; and an interconnect structure on the semiconductor layer, the interconnect structure including metallization patterns electrically coupled to the through via and the silicon device.

Hybrid integrated circuit dies and methods of forming the same

In a color display, a color filter layer includes a dielectric layer with an array of photonic crystals, an electroluminescent material disposed on the color filter layer, and electrodes arranged to electrically energize the electroluminescent material to output white light. Each photonic crystal includes a two-dimensional (2D) array of features. The 2D array of features includes a central cavity within which the features of the 2D array of features are omitted. Each photonic crystal is tuned to a resonant wavelength by a periodicity of the two-dimensional array of features. The array of photonic crystals may include, for example, red, green, and blue photonic crystals arranged to form an array of pixels spanning a display area of the color display, in which each pixel includes at least one red photonic crystal, at least one green photonic crystal, and at least one blue photonic crystal.

Color display with color filter layer comprising two-dimensional photonic crystals formed in a dielectric layer

A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via (TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.

Hybrid bonding technology for stacking integrated circuits

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having a first horizontally extending surface and a second horizontally extending surface above the first horizontally extending surface as viewed in a cross-sectional view. The first horizontally extending surface continuously wraps around an outermost perimeter of the second horizontally extending surface in a closed loop as viewed in a plan-view. A second substrate is disposed over the first substrate and includes a third horizontally extending surface above the second horizontally extending surface as viewed in the cross-sectional view. The second horizontally extending surface continuously wraps around an outermost perimeter of the third horizontally extending surface in a closed loop as viewed in the plan-view.

Techniques for wafer stack processing

A process for fabricating a semiconductor structure is disclosed. The process includes: forming an isolation trench in a substrate; forming a trench fill layer to at least fill the isolation trench in the substrate, the silicon oxide trench fill layer comprising a portion in contact with the substrate below an upper surface of the substrate; exposing a sidewall of the isolation trench and without exposing a bottom of the isolation trench in the substrate; and forming a gate structure over the substrate, wherein the gate structure contacts the sidewall of the isolation trench.

The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.

Semiconductor wafer seal ring having protrusion extending into trench in semiconductor substrate

The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Multi-wafer capping layer for metal arcing protection

The present disclosure relates to a method and an associated process tool. The method includes generating electromagnetic radiation that is directed toward a perimeter of a pair of bonded workpieces and toward a radiation sensor that is arranged behind the perimeter of the pair of bonded workpieces. The electromagnetic radiation is scanned along a vertical axis. An intensity of the electromagnetic radiation that impinges on the radiation sensor is measured throughout the scanning. Measuring the intensity includes recording a plurality of intensity values of the electromagnetic radiation at a plurality of different positions along the vertical axis extending past top and bottom surfaces of the pair of bonded workpieces. A position of an interface between the pair of bonded workpieces is determined based on a maximum measured intensity value of the plurality of intensity values.

Process tool for analyzing bonded workpiece interface

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A dielectric protection layer is along a sidewall of the interconnect structure and along a sidewall and a recessed surface of the substrate. A bottommost surface of the dielectric protection layer rests on the recessed surface of the substrate.

Trim wall protection method for multi-wafer stacking

A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.

Protective wafer grooving structure for wafer thinning and methods of using the same

Growing community of inventors

Hsinchu, Taiwan

Kuo-Ming Wu