Silicon Motion, Inc.

United Microelectronics Corp.

Other

Industrial Technology Research Institute

National Yang Ming Chiao Tung University

Kuang-chao Chen

Kuo-Liang Yeh

Ken-Fu Hsu

Kuang-Chao Chen

Jinn-Horng Lai

Chien-Tung Yue

Ching-Wen Hung

Po-Yu Yang

Ching-Hui Lin

Kung-Lung Cheng

Jyh-Chyurn Guo

Shyue-Ming Jang

Cheng-Hsiung Chen

An-Cheng Chen

Chia-Hsin Chen

Kuo-Chang Wang

Pei-Chen Huang

Yu-Hao Hsu

Mu-Kai Tsai

Chun-Li Lin

Fang-Yun Liu

A semiconductor device includes a substrate, a first transistor disposed on the substrate, a second transistor in proximity to the first transistor on the substrate, at least one interlayer dielectric layer covering the first transistor and the second transistor, a first stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the first transistor, and a second stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the second transistor.

Semiconductor device

The present invention provides a method of generating dummy patterns and calibration kits, including steps of generating devices-under-test (DUTs) using a point of said chip window layer as reference point in a unit cell, generating calibration kits corresponding to the DUTs using the point as reference point in corresponding unit cells, generating DUT dummy patterns for each DUTs individually in the unit cell, copying the DUT dummy patterns in the unit cell to the corresponding calibration kits in the corresponding unit cells using the point as reference point, and merging all of the unit cell and corresponding unit cells into a final chip layout.

Method of generating dummy patterns for device-under-test and calibration kits

Disclosed is a hearing auxiliary device for helping a person with hearing impairment to obtain hearing information. The hearing auxiliary device includes a bone conduct transceiver, a receiver and a driver. The bone conduct transceiver converts a sound raw data to a bone conduct signal. The receiver is installed to an inner ear portion of the person with hearing impairment, and the receiver receives the bone conduct signal and converts the bone conduct signal to a sound restoration signal. The driver sends out a physical signal according to the sound restoration signal, in order to let the person with hearing impairment to obtain a hearing signal.

Hearing auxiliary device and hearing auxiliary processing method

A cochlea hearing aid device for helping users to hear includes a cochlea electrode and a driver circuit. The driver circuit has a casing for installing at a through hole on an eardrum of the user. The cochlea electrode is installed within the cochlea of a user. The driver circuit is connected to the cochlea electrode in order to signal process a voice data and provides a corresponding driving signal for cochlea electrode. Therefore, the neural cells in the cochlea of the user will be stimulated and helped the user to hear.

Cochlea hearing aid fixed on eardrum

An external electronic ear device includes a housing, an external magnet, a microphone, a processing circuit and a wireless signal transmitter circuit. The external magnet is disposed in the housing and attracts a receiver magnet disposed under a scalp of a user. The microphone is disposed in the housing and receives an external sound and generates a sound signal corresponding to the external sound. The processing circuit is disposed in the housing and converts the sound signal into an electrode driving signal. The wireless signal transmitter circuit is disposed in the housing and transmits the electrode driving signal to a cochlear implant device in the cochlear system. The cochlear implant device converts the electrode driving signal into a plurality of electrode currents, and a plurality of electrical pulses are generated in a cochlear nerve of the user through a plurality of electrodes according to the electrode currents.

External electronic ear device and cochlear implant device

A data storage apparatus has a transmission interface, a nonvolatile memory and a controller. The controller records a non-completed flag. When the controller starts a card opening process, the nonvolatile memory is configured under card opening, and the non-completed flag is set non-completed status. When the controller receives a format command form the transmission interface, the nonvolatile memory is formatted and the non-completed flag is set as completed status. When the controller receives a write command, the write data are scrambled before being written to the nonvolatile memory. When in non-completed status, when the controller receives a read command from the transmission interface, no matter whether the data corresponding to the requested address are scrambled, the data are descrambled and descrambled are provided via the transmission interface.

Data storage apparatus for scrambled data and management method thereof

A parameter extraction method for semiconductor devices includes: providing a first multi-finger device and a second multi-finger device, wherein the gate-finger numbers between the first and second multi-finger devices are different; performing an open de-embedding, then the high-frequency test apparatus measuring a first intrinsic gate capacitance of the first multi-finger device and a second intrinsic gate capacitance of the second multi-finger device; calculating a slope according to the first and second intrinsic gate capacitances, and the first and second gate-finger numbers; performing a 3D capacitance simulation for computing the poly finger-end fringing capacitances; utilizing a long channel device for measuring the gate capacitance and extracting the intrinsic gate capacitance, then calculating an inversion channel capacitance per unit area; and computing a delta channel width of the semiconductor device, according to the slope, the poly finger-end fringing capacitance, and the inversion channel capacitance per unit area.

Parameter extraction method for semiconductor device

A method for performing data pattern management regarding data accessed by a controller of a Flash memory includes: when the controller receives a write command, generating a first random function, where the write command is utilized for instructing the controller to write the data into the Flash memory; and adjusting a plurality of bits of the data bit by bit to generate a pseudo-random bit sequence, and writing the pseudo-random bit sequence into the Flash memory to represent the data, whereby data pattern distribution of the data is adjusted. An associated memory device and the controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control the access to the Flash memory and manage a plurality of blocks; and a randomizer arranged to generate a random function. The controller can perform data pattern management.

Method for performing data pattern management regarding data accessed by a controller of a flash memory, and associated memory device and controller thereof

A liquid crystal compound of Formula (1) is provided below: wherein R is hydrogen, linear or branching C1-15 alkyl, linear or branching C1-15 alkyl (wherein any one of &#x2014;CH&#x2014; is replaced by &#x2014;O&#x2014;, &#x2014;S&#x2014;, &#x2014;CO&#x2014;, &#x2014;CO&#x2014;O&#x2014;, or &#x2014;O&#x2014;CO&#x2014;), linear or branching C2-15 alkenyl, or linear or branching C2-15 alkenyl (wherein any one of &#x2014;CH&#x2014; is replaced by &#x2014;O&#x2014;, &#x2014;S&#x2014;, &#x2014;CO&#x2014;, &#x2014;CO&#x2014;O&#x2014;, or &#x2014;O&#x2014;CO&#x2014;), A and B are, independently, cyclohexane, cyclohexane (wherein any one of &#x2014;CH&#x2014; is replaced by &#x2014;O&#x2014; or &#x2014;NH&#x2014;), benzene, or benzene (wherein any one of &#x2014;CH&#x2550; is replaced by &#x2014;N&#x2550;), X is a single bond, &#x2014;CO&#x2014;O&#x2014;, &#x2014;O&#x2014;CO&#x2014;, &#x2014;CHO&#x2014;, &#x2014;OCH&#x2014;, &#x2014;CHCH&#x2014;, &#x2014;C&#x2550;C&#x2014;, &#x2014;C&#x2261;C&#x2014;, &#x2014;CFO&#x2014;, or &#x2014;OCF&#x2014;, Q is oxygen or CH, Y is CF, CFH, or CFH, L, L, and Lare, independently, hydrogen or fluorine, and m is 0, 1, or 2.

Liquid crystal compounds and compositions and liquid crystal displays and photoelectric devices comprising the compounds and compositions

The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a downgrade memory and a controller. The downgrade memory comprises a plurality of blocks, wherein each of the blocks comprises a plurality of pages, each of the pages comprises a plurality of sectors, and some of the sectors are defect sectors. The controller generates a defect table for recording a plurality of defect addresses of the defect sectors in the blocks, receives a plurality of data sectors to be written to the downgrade memory from the host, determines a plurality of first physical sector addresses for storing the data sectors according to the defect table, and sends write commands to the downgrade memory to direct the downgrade memory to write the data sectors to the downgrade memory according to the first physical sector addresses.

Data storage device, controller, and data access method for a downgrade memory

A method for conjecturing the effective size, i.e. the effective width or effective length, of a gate is disclosed. First, a first design gate group including a first gate design width and a first gate design length is provided. Second, an intrinsic gate channel capacitance and an edge capacitance of the first design gate are respectively obtained by calculation. Then a size error, i.e. a width error or a length error is predicted by means of the intrinsic gate channel capacitance and of the edge capacitance to calculate a calculated inversion capacitance and a predicted size deviation. Later, the size error is repeatedly predicted to minimize the predicted size deviation and to optimize the size error to obtain an optimized size error. Afterwards, the effective size of the gate are conjectured by means of the optimized size error.

Method for conjecturing effective width and effective length of gate

A method to extract gate to source/drain and overlap capacitances is disclosed. A first capacitance of a first test key having a reference structure and a second capacitance of a second test key having a novel structure are measured. The second test key may comprise at least a gate formed on an insulation structure, at least a contact formed on the insulation structure aside, and a metal layer formed on the contact. Another embodiment of the second test key may comprise at least a gate formed on the semiconductor substrate, a contact formed aside, and a metal layer formed on the contact. Further another embodiment uses a test key comprising at least an elongated gate and an elongated doping region aside, and only one or a few contacts are formed on an end portion of the elongated doping region.

Growing community of inventors

Hsinchu, Taiwan

Kuo-Liang Yeh