Nan Ya Technology Corporation

Evonik Degussa Gmbh

Kuo Hui Su

Yi Chun Chen

Duy Vu Pham

Hsien Wen Liu

Chiang Hung Lin

Yi Jung Chen

The present invention relates to a novel thin film transistor (TFT) comprising a substrate () with a gate electrode layer () deposited and patterned thereon and a gate insulator layer () deposited on the gate electrode layer and the substrate, characterized in that the transistor further comprises (i) a carrier injection layer () arranged above the gate insulator layer, (ii) a source/drain (S/D) electrode layer () deposited on the carrier injection layer, and (iii) a semiconductor layer (), methods for the production of such novel TFTs, devices comprising such TFTs, and to the use of such TFTs.

Low contact resistance thin film transistor

A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer.

Semiconductor device and method of manufacturing the same

A method for fabricating a gate dielectric layer comprises the steps of: forming a dielectric layer on a semiconductor substrate; performing a nitrogen treating process to form a nitride layer on the dielectric layer; and performing a thermal treating process at 1150-1400&#xb0; C. for a period of 400-800 milliseconds, to form a gate dielectric layer. A step of forming a gate layer on the gate dielectric layer may be performed to form a gate structure.

Growing community of inventors

Taipei, Taiwan

Kuo Hui Su