Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo Hui Chang

Mu-Tsang Lin

Chen Liang Chang

Che-Cheng Chang

Chang-Yin Chen

Tung-Wen Cheng

Chia-Ching Lee

Zhe-Hao Zhang

Wei-Chiang Hung

Shing Lee

Chi-chun Peng

Ching Lang Yen

Hsiang-Yu Tsai

Ryder Su

Young-Wei Lin

Yu Liang Huang

Po-Yu Su

Jung-Wang Lu

Ping-Chung Liu

Chi-Chun Peng

At least one embodiment, a vacuum chuck includes a moisture gate structure that allows for moisture to escape to reduce an amount of warpage in a workpiece when present on the vacuum chuck. The moisture gate structure includes a base portion that extends laterally outward from a central vacuum portion of the vacuum chuck, and a plurality of protrusions are spaced apart from the central vacuum portion and extend outward from the base portion. End surfaces of the plurality of protrusions contact a backside surface of the workpiece (e.g., a wafer on a carrier) when the workpiece is present on the vacuum chuck. The vacuum chuck may further include one or more guide portions that act as guides such that the workpiece remains properly aligned and within position when present on the vacuum chuck.

Vacuum chuck

A method of removing a sacrificial substructure from a support structure is disclosed. The method includes receiving the support structure, where the support structure has the sacrificial substructure connected thereto, the sacrificial substructure having functioning electrical devices removed therefrom. The method also includes applying a barrier to the sacrificial substructure, puncturing the sacrificial substructure with a puncture plate to secure the sacrificial substructure to the puncture plate, and detaching the sacrificial substructure from the support structure by moving the puncture plate with respect to the support structure.

De-tape tool

The present disclosure provide a semiconductor structure, including a substrate having a top surface; a gate over the substrate, the gate including a footing region in proximity to the top surface, the footing region including a footing length laterally measured at a height under 10 nm above the top surface; and a spacer surrounding a sidewall of the gate, including a spacer width laterally measured at a height of from about 10 nm to about 200 nm above the top surface. The footing length is measured, along the top surface, from an end of a widest portion of the footing region to a vertical line extended from an interface between a gate body and the spacer, and the spacer width is substantially equal to or greater than the footing length.

Semiconductor structure and manufacturing method of the same

Provided is a semiconductor device including a gate electrode, source and drain regions, and a spacer. The gate electrode is located over a substrate, and an angle of a base corner of the gate electrode is greater than 90 degrees. The source and drain regions are located in the substrate at sides of the gate electrode. The spacer is located at a sidewall of the gate electrode.

Semiconductor device and manufacturing method thereof

A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; and a stress memorization technology (SMT) sidewall spacer over a sidewall of the gate stack. The gate stack includes a gate dielectric layer over the semiconductor substrate and a gate electrode over the gate dielectric layer. The SMT sidewall spacer provides a stress for a channel region beneath the gate stack.

Semiconductor structure and manufacturing method thereof

A method of improving the yield and performance of IC devices fabricated on a semiconductor wafer is disclosed. The method includes fabricating via plugs in via openings provided in an intermetal dielectric (IMD) layer on a wafer, subjecting the wafer to CMP to isolate the via plugs, immersing and soaking the wafer in deionized (DI) water, and drying the wafer using isopropyl alcohol, typically in a Marangoni-type dryer. The Marangoni IPA drying step prevents the formation of static electricity on the wafer, and thus, prevents the adherence of small charged particles to the wafer. As a result, the yield of IC devices fabricated on the wafer, as well as the performance of the devices, is enhanced.

Method of improving device performance

Growing community of inventors

Taoyuan County, Taiwan

Kuo Hui Chang