Taiwan Semiconductor Manufacturing Comp. Ltd.

Parabellum Strategic Opportunties Fund LLC

Kuo-Hua Pan

Ta-Chun Lin

Jhon Jhy Liaw

Chun-Sheng Liang

Hsin-Che Chiang

Min-Yann Hsieh

Jhon-Jhy Liaw

Hua Feng Chen

Chun-Jun Lin

Yu-San Chien

Wen-Che Tsai

Wei-Chih Kao

Jyun-Ming Lin

Kuan-Lin Yeh

Chih-Yung Lin

Shien-Yang Wu

Mu-Chi Chiang

Buo-Chin Hsu

Hua-Feng Chen

Chun-Hung Chen

Chih-Hung Hsieh

Shu-Hui Wang

Ming-Heng Tsai

Kuang-Cheng Tai

Yu-Jen Chang

Je-Wei Hsu

Tien-Shao Chuang

Java Wu

Chen-Huang Peng

Sai-Hooi Yeong

Chung-Te Lin

Li-Chun Tien

Tzu-Chiang Chen

Hung-Li Chiang

Chao-Ching Cheng

I-Sheng Chen

Hong-Chen Cheng

Shih-Syuan Huang

Ju-Yuan Tzeng

Chu-Wei Hu

Hung-Jen Liao

Cheng Hung Lee

Jung-Hsuan Chen

Hsien-Chin Lin

Ming-Yi Lee

C H Wu

Ming-Che Chen

Ken Liao

Syun-Ming Jang Jang

Harry Chuang

Yung-Chih Wang

Jeng-Ya David Yeh

Yi-Fang Pai

Chih-Yang Yeh

Wen-Huei Guo

Chin-Shan Hou

Shun-Jang Liao

Hou-Ju Li

Chin-Hsiung Ho

Chien-Chi Tien

Jyh-Haur Wang

Kuei-Ming Chang

Chih-Chiang Wang

Rei-Jay Hsieh

Yi-Ching Lin

Yu-Chang Liang

Carlos Hernando Diaz

Jyun-Yang Shen

Wen-Li Chiu

Yun-Hsiu Chen

Shi-Wei Chang

Augus Tai

Chun-Wing Yeung

Wen-Chiang Hong

A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.

Isolation structure for isolating source/drain region structure from adjacent source/drain structure

A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.

Semiconductor device structure including forksheet transistors and methods of forming the same

A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Contact plugs and methods forming same

A method includes depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and with an epitaxial growth process, filling the trench with the second type of semiconductor material. The method further includes patterning the semiconductor stack within the first region to form a nanostructure stack, patterning the second type of semiconductor material within the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure.

Hybrid nanostructure and fin structure device

Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

Vias for cobalt-based interconnects and methods of fabrication thereof

A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.

Reducing parasitic capacitance in field-effect transistors

A method for manufacturing a semiconductor device is provided. The method includes forming first and second semiconductor fins; forming first and second gate structures respectively over first regions of the first and second semiconductor fins; forming a first dummy spacer at a sidewall of the first gate structure adjacent a second region of the first semiconductor fin; etching a first source/drain recess in the second region of the first semiconductor fin; forming a n-type source/drain epitaxial structure in the first source/drain recess; forming a second dummy spacer at a sidewall of the second gate structure adjacent a second region of the second semiconductor fin, wherein the second dummy spacer has a thickness less than that of the first dummy spacer; etching a second source/drain recess in the second region of the second semiconductor fin; and forming a p-type source/drain epitaxial structure in the second source/drain recess.

Semiconductor device and manufacturing method thereof

Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes receiving a workpiece comprising a first semiconductor element and a second semiconductor element, and a dielectric fin disposed between the first semiconductor element and the second semiconductor element. The method also includes forming a masking layer directly over the dielectric fin, etching the first semiconductor element and the second semiconductor element to form a first recess and a second recess, and forming a first source/drain feature and a second source/drain feature in the first recess and the second recess, respectively. By employing a masking layer and patterning the masking layer to have different widths, a parasitic resistance and a parasitic capacitance of the semiconductor structure may be adjusted accordingly, and undesirably bridging between two adjacent epitaxial source/drain features may be prevented.

Semiconductor strutures with dielectric fins

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region of a first conductivity type. The semiconductor device structure also includes a first fin structure and an adjacent second fin structure formed in and protruding from the first well region. The semiconductor device structure also includes a first isolation structure formed in the first well region between the first fin structure and the second fin structure. A first sidewall surface of the first fin structure faces to a second sidewall surface of the second fin structure. The first sidewall surface and the second sidewall surface each extend along at least two directions from a bottom of the first isolation structure to a top of the first isolation structure.

Isolation with multi-step structure

Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.

Semiconductor structure with extended contact structure

Structures and formation methods of a semiconductor device are provided. The method includes forming a first dummy gate structure across a first fin in a first transistor region of a semiconductor substrate and a second dummy gate structure across a second fin in a second transistor region of the semiconductor substrate. The method also includes selectively introducing atomic or ionic species into the second fin on opposite sides of the second dummy gate structure and etching portions of the first and second fins, so as to form first and second recesses. Each recess is in the respective fin on a side of the respective dummy gate structure. The first recess has a different depth than the second recess. The method further includes forming first and second source/drain features in the first and second recesses, respectively.

Semiconductor device having different source/drain junction depths and fabrication method thereof

Provided is a semiconductor device including a substrate, one hybrid fin, a gate, and a dielectric structure. The substrate includes at least two fins. The hybrid fin is disposed between the at least two fins. The gate covers portions of the at least two fins and the hybrid fin. The dielectric structure lands on the hybrid fin to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the hybrid fin. The hybrid fin includes a first portion, disposed between the two segments of the gate; and a second portion, disposed aside the first portion, wherein a top surface of the second portion is lower than a top surface of the first portion.

Semiconductor device and method of forming the same

A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer structure over a sidewall of the gate stack. The method includes forming a source/drain structure in and over the substrate, wherein a portion of the spacer structure is between the source/drain structure and the gate stack. The method includes partially removing the outer layer, wherein a first lower portion of the outer layer remains between the source/drain structure and the gate stack. The method includes partially removing the middle layer, wherein a second lower portion of the middle layer remains between the source/drain structure and the gate stack.

Semiconductor device structure and method for forming the same

A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

Isolation structure for preventing unintentional merging of epitaxially grown source/drain

A semiconductor device includes a substrate, an epitaxial structure over the substrate, a conductive structure, and a dielectric liner. The conductive structure extends from within the epitaxial structure to above the epitaxial structure. The dielectric liner extends along a sidewall of the conductive structure. The dielectric liner has a top end capped by the conductive structure.

Semiconductor device with source/drain contact

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Hsinchu, Taiwan

Kuo-Hua Pan