Lucent Technologies Inc.

At+t Corp.

At&t Bell Laboratories

Agere Systems Guardian Corp.

American Telephone & Telegraph Co., At&t Bell Laboratories

Other

American Telephone and Telegraph, Co.

Kuo-Hua Lee

Chen-Hua D Yu

Janmye Sung

Chun-Ting Liu

Chih-Yuan Lu

Ruichen Liu

William J Nagy

Frederick Harrison Fischer

Nur Selamoglu

William John Nagy

David S Yaney

Sailesh Mansinh Merchant

Simon John Molloy

Kurt George Steiner

Samir Chaudhry

Alan Sangone Chen

Taeho Kook

Ran-Hong Yan

Michael Scott Carroll

Yih-Feng Chyan

Daniel Joseph Vitkavage

Thomas Evans Adams

Steven J Hillenius

Larry Bruce Fritzinger

Horng-Dar Lin

Larry B Fritzinger

Chorng-Ping Chang

Chung-Ting Liu

Samuel E Polanco

An improved method of capacitor formation is disclosed. A dielectric is etched with an etch recipe which creates grooves within an opening. The opening is filled with metal which conforms to the grooves, thereby creating a capacitor's lower plate with increased surface area. The metal is later surrounded with dielectric and metal, which forms respectively the capacitor's dielectric and upper plate.

Grooved capacitor structure for integrated circuits

The present invention provides a static random-access memory (SRAM) device that comprises a substrate having an insulator and a gate formed thereover, where the insulator electrically insulates the gate from the substrate, and a local conductive layer that is formed on the gate structure and that extends from the gate and onto the substrate. The local conductive layer is connectable to a conductive interconnect structure to connect the gate electrically to an other portion of the SRAM device. The SRAM device, in one embodiment, is part of a complementary metal oxide semiconductor (CMOS). However, it will be appreciated by those who are of ordinary skill the art that the present invention may be used in various types of metal oxide semiconductors and similar semiconductor devices in general. Therefore, in an aspect of the present invention, there is provided a local conductive interconnect structure that provides a electrical path to which the gate may be electrically connected to other portions of the SRAM device without the need of multiple interconnect structures found in prior art devices. Thus, the overall cell size of the SRAM device may be substantially decreased such that it can be used in applications that require smaller cell sizes.

Static random-access memory device having a local interconnect structure

The present invention provides for use with an integrated circuit, an embedded memory having a transistor in contact with an interconnect formed within a dielectric layer overlaying the transistor. In one embodiment, the embedded memory comprises a capacitor located on the dielectric layer that contacts the interconnect. In this particular embodiment, the capacitor includes a first electrode located on the interconnect wherein the first electrode is a layer of aluminum, aluminum alloy or titanium nitride and substantially free of a titanium layer. In one advantageous embodiment, the first electrode layer is an aluminum alloy. Moreover, the thickness of the first electrode may, of course, varying depending on the design. However, in one is particular embodiment, the first electrode may have a thickness ranging from about 10 nm to about 50 nm.

Capacitor having aluminum alloy bottom plate

A bipolar fabrication process, illustratively suited for integration into a conventional CMOS process to thereby form a BiCMOS integrated circuits is disclosed. The collector and base are formed through multiple implants and a single masking step to thereby provide a continuous low resistance collector region.

Process for making bipolar having graded or modulated collector

A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.

Process for producing multi-level metallization in an integrated circuit

A novel process for forming a window, illustratively, an emitter window BiCMOS process is disclosed. An anisotropic etch followed by an isotropic etch to open the window is disclosed. The isotropic etch prevents contamination of the substrate by the anisotropic etching process.

Integrated circuit fabrication

Embodiments of the invention include a dynamic random access memory (DRAM) and method for making a DRAM in which the capacitive elements are fabricated to be planar or nearly planar and to be located above the metal regions (M1) that connect the sources and drains of the transistor through conductive windows (W1). Embodiments of the invention fabricate the DRAM by forming a transistor on a suitable substrate in the appropriate manner and depositing a first oxide layer that is subsequently planarized by suitable technique. A window is then formed within the oxide layer and a conductive plug is formed within the window. A first patterned metal region, which functions as a memory cell bit line or as a coupler between conductive plugs, is then formed on the oxide layer. A second oxide layer is formed thereon and appropriate windows and conductive plugs are formed therein. Then, a capacitor is formed thereon in a planar or near planar configuration. A second patterned metal region is formed on the capacitor. A third oxide layer is formed thereon and appropriate windows and conductive plugs are formed therein. A third patterned metal region is then formed on the oxide layer. Finally, a fourth oxide layer is deposited and planarized in an appropriate manner. Alternatively, a trench is formed within the second oxide layer around the conductive plug prior to formation of the capacitor thereon. Also, in alternative embodiments, conductive plugs are coupled without the use of patterned metal regions. According to embodiments of the invention, the DRAM fabrication method and the DRAM formed thereby are more conducive than conventional fabrication methods to the use of planarization techniques such as chemical mechanical polishing (CMP). The planar or near planar configuration of the various oxide layers and various DRAM elements formed therein lend themselves well to planarization techniques.

Metal to metal capacitor apparatus and method for making

A gate contact to a field effect transistor is opened over the source/drain region by forming polysilicon plugs between the gate structure, which has a nitride top layer, and the field oxide regions. The contacts are formed by oxidizing and etching the gate structure and the polysilicon plugs. An oxide layer may be deposited prior to the etching. The latter step opens a gate contact but does not expose the silicon in the plug because the different oxidation rates of the polysilicon plug and the material on top of the gate structure create oxide layers having different thicknesses. The nitride is now removed and contacts formed to the gate structure.

Method for forming self aligned polysilicon contact

A self aligned contact to the substrate in the region between two gate electrodes is formed by depositing a conformal dielectric layer and patterning to form a contact window. The conductive elements of the gate electrode are not contacted because of etch rate differentials between the conformal dielectric and the insulating elements of the gate structure.

Self-aligned contact window

A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adjacent double or triple layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.

FET with gate spacer

The longitudinal edges of the overlying channel layer of a thin-film transistor are substantially aligned with the longitudinal edges of the underlying polysilicon gate layer. As a result of this line-on-line arrangement of the channel and gate layers, integration area is minimized so that optimum integration density is achieved. Source-to-drain on current is increased as the result of the increased channel width gained from the sidewall section of the polysilicon gate, which may occur as a result of the permissible lateral extension of the body (channel) layer over one longitudinal edge of the channel gate layer due to a misalignment in lithography or processing delta.

Thin film transistor having increased effective channel width

A method of semiconductor fabrication having applicability to forming contacts to sources and drains especially in SRAM applications is disclosed. A dielectric and an overlying polysilicon conductor are formed and patterned thereby exposing a semiconductor substrate. A silicide layer is deposited, thereby contacting the polysilicon layer and the substrate. Subsequent patterning of the silicide layer using an oxide hard mask provides electrical contact between the polysilicon layer and the substrate without the risk of trenching into the substrate.

Integrated circuit fabrication having contact opening

A complementary device consisting of a PMOS TFT transistor and an NMOS FET transistor uses a conducting layer to shunt drain regions of the transistors to eliminate any detrimental diode or p-n junction effects. The use of the conducting layer significantly improves the current drive capabilities of the PMOS TFT when the complementary device is used to design SRAM cells with NMOS pull-down transistors.

Complementary TFT devices with diode-effect elimination means

A method of field oxide formation which creates field oxides of comparatively uniform height between differently-spaced oxidation masks is disclosed. A patterned oxidation mask, typically silicon nitride, (possibly with underlying polysilicon) is formed. A blanket layer of polysilicon is formed and etched back, thereby filling spaces between closely-spaced portions of the oxidation mask and fillets between less-closely spaced portions. A thermal oxidation is performed to produce a field oxide. The field oxide has comparatively uniform height despite differences in oxidation mask spacing.

Poly-buffered LOCOS

An integrated circuit is described which has an electrical contact formed between a metallic silicide and .alpha.:Si. The method of integrated circuit manufacturing comprising the steps of: forming a layer of a metallic silicide; depositing a layer of .alpha.:Si on said metallic silicide at a temperature less than the recrystallization temperature; and increasing the conductivity of at least selected portions of said .alpha.:Si by ion implanting a species having the peak of its spatial distribution spaced from the .alpha.:Si-Silicide interface and the .alpha.:Si surface.

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Lower Macungie Township, PA, United States of America

Kuo-Hua Lee