Advanced Semiconductor Engineering, Inc.

China Steel Corporation

Kuo-Hua Chen

Chi-Tsung Chiu

Hui-Ying Hsieh

Ming-Chiang Lee

Hui Hua Lee

Tsung-Hsun Lee

Chen-Chuan Fan

Chun Hao Chiu

Kuan-Neng Chen

Jen-Kuang Fang

Ming-Hung Chen

Jin-Chern Chiou

Chin-Li Kao

Chih-Wei Chang

Chih-Yi Huang

Ying-Te Ou

Kuo-Pin Yang

Tang-Yuan Chen

Chieh-Chen Fu

Dao-Long Chen

Cheng Yuan Chen

Tzu-Hua Lin

Yan-Pin Huang

Mi-Cheng Cheng

She-Hong Cheng

Chung-Yung Wu

Huang-Chuan Chang

Jiunnjyh Wang

A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.

Semiconductor device package

A semiconductor package structure includes a base, at least one semiconductor element, a first dielectric layer, a second dielectric layer and a circuit layer. The semiconductor element is disposed on the base and has an upper surface. The first dielectric layer covers at least a portion of a peripheral surface of the semiconductor element and has a top surface. The top surface is non-coplanar with the upper surface of the semiconductor element. The second dielectric layer covers the semiconductor element and the first dielectric layer. The circuit layer extends through the second dielectric layer to electrically connect the semiconductor element.

Semiconductor package structure and method for manufacturing the same

The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments.

Semiconductor package structure including die and substrate electrically connected through conductive segments

The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a leadframe and a semiconductor die. The leadframe includes a main portion and a protrusion portion. The semiconductor die is bonded to a first surface of the main portion. The protrusion portion protrudes from a second surface of the main portion. The position of the protrusion portion corresponds to the position of the semiconductor die.

A substrate structure is provided. The substrate structure includes a number of traces, a substrate core, a number of first metal tiles, a number of second metal tiles, a number of first electrically-functioning circuits, and a number of second electrically-functioning circuits. The substrate core has a first surface and a second surface opposite to the first surface. The traces, the first metal tiles, and the first electrically-functioning circuits are disposed on the first surface and add up to a first metal structure proportion, and the second metal tiles and the second electrically-functioning circuits are disposed on the second surface and add up to a second metal structure proportion. The difference between the first metal structure proportion and the second metal structure proportion is within 15%.

Substrate structure and package structure using the same

A semiconductor device package includes a substrate and a semiconductor device disposed on a surface of the substrate. The semiconductor device includes a first contact pad and a second contact pad disposed on an upper surface of the semiconductor device. The semiconductor device package further includes a conductive bar disposed on the first contact pad, and a conductive pillar disposed on the second contact pad. A method of making a semiconductor device package includes (a) providing a substrate; (b) mounting a semiconductor device on the substrate, wherein the semiconductor device comprises a first contact pad and a second contact pad on an upper surface of the semiconductor device; (c) forming a dielectric layer on the substrate to cover the semiconductor device; (d) exposing the second contact pad by forming a hole in the dielectric layer; and (e) applying a conductive material over the dielectric layer and filling the hole.

Semiconductor device package and method of making the same

The disclosure relates to a semiconductor bonding structure and process and a semiconductor chip. The semiconductor bonding structure includes a first pillar, a first interface, an intermediate area, a second interface and a second pillar in sequence. The first pillar, the second pillar and the intermediate area include a first metal. The first interface and the second interface include the first metal and an oxide of a second metal. The content percentage of the first metal in the first interface and the second interface is less than that of the first metal in the intermediate area.

Semiconductor bonding structure

The present invention provides a neural sensing device and method for making the same. The neural sensing device includes a base, an integrated circuit portion, a plurality of microprobes and at least one conductive via. The base has an active surface and a backside surface. The integrated circuit portion is disposed on the active surface of the base. The microprobes protrude from the backside surface of the base. The through silicon via is disposed in the base and electrically connects the integrated circuit portion and the microprobes. Each of the microprobes includes an isolation layer partially covering a conductive layer.

Neural sensing device and method for making the same

The present invention provides a neural sensing device and method for making the same. The neural sensing device includes a base, an integrated circuit portion and a plurality of microprobes. The base has an active surface and a backside surface. The integrated circuit portion is disposed on the active surface of the base. The microprobes protrude from the backside surface of the base. The conductive vias are disposed in the microprobes and electrically connected to the integrated circuit portion.

A substrate structure and a package structure using the same are provided. The substrate structure includes a number of traces, a substrate core and a number of first metal tiles. The substrate core has a first surface and a second surface opposite to the first surface. The first metal tiles are disposed on one of the first surface and the second surface, the minimum pitch between adjacent two of the first metal tiles is the minimum process pitch.

The present invention relates to a silicon substrate having through vias and a package having the same. The silicon substrate includes a substrate body, a plurality of through vias and at least one heat dissipating area. The substrate body has a surface, and the material of the substrate body is silicon. The through vias penetrate the substrate body, and each of the through vias has a conductive material therein. The heat dissipating area is disposed on the surface of the substrate body and covers at least two through vias. The heat dissipating area is made of metal, and the through vias inside the heat dissipating area have same electrical potential. Thus, the heat in the through vias is transmitted to the heat dissipating area, and since the area of the heat dissipating area is large, the silicon substrate has good heat dissipation efficiency.

Silicon substrate having through vias and package having the same

A package structure with an embedded die includes a core layer, a first build-up wiring structure, and a second build-up wiring structure. The core layer has a first surface and a second surface opposite thereto. Besides, the core layer includes a first dielectric layer, a leadframe, a die, a first signal layer, and a second signal layer. The die is disposed on and electrically connected to the leadframe. The die and the leadframe are embedded in the first dielectric layer. The first signal layer is disposed on an upper surface of the first dielectric layer and electrically connected to the leadframe. The second signal layer is disposed on a bottom surface of the first dielectric layer and electrically connected to the leadframe. The first and the second build-up wiring structures are disposed on the first and the second surfaces of the core layer, respectively.

Package structure with embedded die and method of fabricating the same

A package structure and an electronic device using the same are provided. The package structure includes a chip module and a cover. The chip module covered by the cover is used for receiving a first signal. The chip module includes a substrate, a heat sink and a first chip. The substrate has a first surface, a second surface and an opening. The first surface is opposite to the second surface. The opening penetrates the first surface and the second surface. The heat sink is disposed on the first surface of the substrate and covers the opening. The first chip is disposed on the heat sink and is positioned inside the opening. A bottom surface of the first chip flatly contacts the heat sink. The cover has a window element. The first signal passes through the window element to contact with the chip module.

Package structure and electronic device using the same

A compact camera module (CCM) substantially includes a substrate, a sensor chip and a lens module. The substrate has a surface defining a chip-attached area for attaching the sensor chip and a module-secured area for mounting the lens module. A check point is defined in the chip attached area. The module-secured area surrounds the chip-attached area. The substrate includes a plurality of connecting pads and a plurality of check bars disposed outside the chip-attached area, wherein the perpendicular bisectors of the check bars intersect with each other at a point aligning with the check point. Accordingly, a self-check step can be performed to check the center of the sensor area of the sensor chip in accordance with the intersection point after a chip is attached.

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Kaohsiung, Taiwan

Kuo-Hua Chen