Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo-Hsien Cheng

Ying-Lang Wang

Chen-Jong Wang

Chien-Chih Chou

Chien-Chih Chen

Ting-Chun Wang

Chin-Szu Lee

Chue-San Yoo

Cheng-Yi Wu

Wei-Li Chen

Sheng-Yuan Lin

Hung-Che Liao

Jian-Shin Tsai

Chao-Ching Chang

Miao-Cheng Liao

Chen-Peng Fan

Min-Hui Lin

Mu-Han Cheng

Shao-Ta Hsu

Chi-Di An

Chen-Mei Fan

Jer-Yuan Sheu

Cheng Kun Lin

Tsung-Yi Yang

Cheng-Chao Lin

Chung-Yu Hsieh

Wen Zen Chiu

Shih Hui Chang

Wen Jan Lin

Manikandan Arumugam

Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first conductive structure disposed within a first layer of the semiconductor structure. The semiconductor structure includes a dielectric structure disposed within a second layer of the semiconductor structure, with the second layer being disposed on the first layer. The semiconductor structure includes a second conductive structure disposed within a recessed portion of the dielectric structure that extends to the first conductive structure, with the second conductive structure having a concave recessed portion on a top surface of the second conductive structure. The semiconductor structure includes multiple layers of conductive material disposed within the concave recessed portion of the second conductive structure.

Semiconductor structure and manufacturing method thereof

A memory cell includes a selector, a fuse connected to the selector in series, a contact etch stop layer formed on the selector and the fuse, a bit line connected to the fuse, and a word line connected to the selector. The contact etch stop layer includes a high-k dielectric for improving the ability of capturing the electrons, thus the retention time of the memory cell is increased.

Memory cell and fabricating method thereof

An MIM structure and method for forming the same the method including forming a bottom conductive electrode overlying a semiconducting substrate; forming a first protection layer on the conductive electrode; forming a dielectric layer on the first protection layer; and, forming an upper conductive electrode on the dielectric layer to form a metal-insulator-metal (MIM) structure.

MIM structure and fabrication process with improved capacitance reliability

Faults occurring in the operation of a rapid thermal process system are detected and dynamically controlled in-situ. A data set is generated which represents the power applied to heating elements which are spatially arranged in a plurality of zones. The data is converted to a sequence of fractions respectively representing the power applied to each zone relative to the total applied power. The fractions are sequentially arranged and a least squares straight line fit for the fractions is calculated. The slope of the calculated straight line fit is used in a statistical process control system to determine whether a fault has occurred, and to make appropriate corrections in process control parameters, such as the length of time the process is carried out.

Method of detecting and controlling in-situ faults in rapid thermal processing systems

A method is provided to prevent the forming of a high de-focusing ledge or step on the back side of a substrate or a semiconductor wafer in order to improve the photolithographic process steps in semiconductor manufacturing. In semiconductor manufacturing, various processes are performed to form various dielectric and metal layers on the front side of wafers. However, some of these materials deposit on the back side of the wafer as well. These unwanted deposits result in contaminants that break off from the back side, causing reliability problems. Those that do stay on, on the other hand, cause irregular topology, thus affecting the focusing of stepper equipment during photolithographic processes. It is disclosed in the present invention a method of forming an oxide layer which prevents the forming of such de-focusing steps on the back side of a wafer.

Prevent defocus issue on wafer with tungsten coating on back-side

In a CVD vacuum chamber processing system for depositing a blanket of refractory material, such as tungsten, upon a frontside of a semiconductor wafer, an inert gas, such as argon is directed to the backside of the wafer in a manner so as to prevent the chamber reaction gases from reacting with polysilicon or other materials on the backside of the wafer as well as to prevent the deposition of the blanket material on the backside of the wafer. This method alleviates the problems of particulate generation and loss of wafer backside datum surface due to the inadvertent buildup of unwanted materials. The wafer is placed on a heater platen and is secured by a specified range of vacuum pressures. The wafer is exposed to specified ranges of chamber pressure during the deposition phase. During the purge phase, the chamber pressure is reduced and the wafer chucking pressure is increased to a specified range. The method is terminated with the equalization of pressure between the front and backside of the wafer.

Recipe design to prevent tungsten (W) coating on wafer backside for those wafers with poly Si on wafer backside

A process for fabricating a tungsten plug, in a deep, small diameter opening, featuring a novel adhesive-barrier composite layer, located along the sides of the deep, small diameter opening, has been developed. The process features the use of a first titanium nitride barrier layer, deposited on an underlying titanium adhesive layer, via chemical vapor deposition procedures, used to enhance the conformality properties of the first titanium nitride barrier layer. A second titanium nitride barrier layer is then deposited, via plasma vapor deposition procedures, protecting the underlying CVD titanium nitride layer from the environment, while providing an improved surface for subsequent nucleation of a CVD tungsten layer.

Barrier metal composite layer featuring a thin plasma vapor deposited

A method for forming a silicon nitride/silicon oxide (NO) layer within a microelectronics fabrication, and the microelectronics fabrication having the silicon nitride/silicon oxide (NO) layer formed therein. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a first silicon nitride layer through a first deposition method. There is then formed upon the first silicon nitride layer a second silicon nitride layer through a second deposition method. Finally, there is annealed thermally in an oxidizing environment the first silicon nitride layer and the second silicon nitride layer to form therefrom a silicon nitride/silicon oxide (NO) layer. The silicon nitride/silicon oxide (NO) layer may be formed with optimized resistivity properties at a reduced thermal annealing temperature and/or a reduced thermal annealing exposure time in comparison with an otherwise equivalent silicon nitride/silicon oxide (NO) layer formed through thermal annealing a single silicon nitride layer of thickness equivalent to the thickness of the first silicon nitride layer plus the thickness of the second silicon nitride layer. When formed upon a silicon oxide dielectric layer in turn formed upon a first capacitor plate within a capacitor within an integrated circuit, there may be formed employing the silicon nitride/silicon oxide (NO) layer a silicon oxide/silicon nitride/silicon oxide (ONO) capacitive dielectric layer.

Multi-layer silicon nitride deposition method for forming low oxidation

A process for fabricating a polycide SAC structure, for a MOSFET device, has been developed. This process features a polycide SAC structure, comprised of tungsten silicide on in situ doped polysilicon, using tungsten hexafluoride and dichlorosilane as reactants for deposition of tungsten silicide. A first thermal anneal treatment is performed prior to polycide patterning, supplying protection to exposed tungsten silicide sides, during the patterning procedure. A second thermal anneal treatment is performed after polycide patterning, and prior to a silicon oxide deposition, offering protection to the exposed top surface of tungsten silicide, during the silicon oxide deposition.

Two step thermal treatment procedure applied to polycide structures

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Tainan, Taiwan

Kuo-Hsien Cheng