Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo-Feng Yu

Jian-Hao Chen

Chun Hsiung Tsai

Shahaji B More

Chun-Hsiung Tsai

Cheng-Yi Peng

Chia-Wei Chen

Shan-Mei Liao

Kei-Wei Chen

Hui-Chi Chen

Yu-Ming Lin

Wen-Hung Huang

Clement Hsingjen Wann

Yen-Ming Chen

Yung-Hsiang Chan

Ziwei Fang

Shih-Chieh Chang

Shih-Hao Lin

Huai-Tei Yang

Shih-Hang Chiu

Kuei-Lun Lin

Shu-Wei Chung

Chih-Yu Hsu

Feng-Cheng Yang

Jian-Hsing Lee

Da-Wen Lin

Shyue-Shyh Lin

Chia-Yu Lu

Ming-Hsi Yeh

Da-Yuan Lee

Chien-Tai Chan

Wei-Cheng Wang

Chih-Wei Lee

Hsin-Han Tsai

Yen-Ju Chen

Wei Cheng Hsu

Wei-Yang Lee

Tung-Heng Hsieh

Chien-Hao Chen

Chung-Chiang Wu

Hsien-Ming Lee

Chia-Ching Lee

Hung-Chin Chung

Ya-Yun Cheng

Yin-Pin Wang

Chin-Shan Hou

Tsung-Ta Tang

Yu-Chia Liang

Cheng Hong Yang

Mei-Yun Wang

Chih-Hsin Ko

Jaw-Juinn Horng

Chung-Hui Chen

Chia-Pin Lin

King-Yuen Wong

Jiaw-Ren Shih

Chandrashekhar Prakash Savant

Yi-Hsun Wu

Chih-Hung Wang

Zoe Chen

Chun-Chih Cheng

Hsueh-Ju Chen

Fu Chin Yang

An-Hung Tai

Yi-Cheng Tsai

Dun-Nian Yaung

Chi On Chui

Chang-Yun Chang

Yi-Tang Lin

Xiong-Fei Yu

Ming-Hsiang Song

Shao-Chang Huang

Chien-Yuan Chen

Chih-Hao Yu

Ming-Te Chen

Kuan-Ting Liu

Hsien-Chin Lin

Tong-Chern Ong

Cheng-Hao Hou

Ming-Chi Huang

Juing-Yi Wu

Shu-Han Chen

Jun He

Jer-Fu Wang

Yuh-Ta Fan

Hsiu-Hao Tsao

Shu-Chuan Lee

Hoong Shing Wong

Chi-Sheng Lai

Tsung-Da Lin

Yu-Jiun Peng

Jo-Chun Hung

Yao-Teng Chuang

Chang-Jhih Syu

Wei-Chen Hsiao

Hui-Ting Tsai

Chong-Gim Gan

Cs Tang

Cheng-Chieh Tu

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

Post gate dielectric processing for semiconductor device fabrication

In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode formed over a channel region, a first gate dielectric layer is formed over the channel region in the gate space, a second gate dielectric layer is formed over the first gate dielectric layer, one or more conductive layers is formed on the second gate dielectric layer, the second gate dielectric layer and the one or more conductive layers are recessed, an annealing operation is performed to diffuse an element of the second gate dielectric layer into the first gate dielectric layer, and one or more metal layers are formed in the gate space.

Method of manufacturing semiconductor devices and semiconductor devices

A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.

Forming low-resistance capping layer over metal gate electrode

An n-type field effect transistor includes semiconductor channel members vertically stacked over a substrate, a gate dielectric layer wrapping around each of the semiconductor channel members, and a work function layer disposed over the gate dielectric layer. The work function layer wraps around each of the semiconductor channel members. The n-type field effect transistor also includes a WF isolation layer disposed over the WF layer and a gate metal fill layer disposed over the WF isolation layer. The WF isolation layer fills gaps between adjacent semiconductor channel members.

Metal gates for multi-gate devices and fabrication methods thereof

A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.

Device providing multiple threshold voltages and methods of making the same

A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.

Semiconductor device with non-conformal gate dielectric layers

A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.

Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same

A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Semiconductor device and method of manufacture

A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.

Semiconductor device structure and methods of forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a cap layer over the gate stack. The semiconductor device structure includes a protective layer over the cap layer, wherein a lower portion of the protective layer extends into the cap layer. The semiconductor device structure includes a contact structure passing through the protective layer and the cap layer.

Semiconductor device structure and method for forming the same

A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Multi-layer high-k gate dielectric structure

A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.

Semiconductor structure and manufacturing method of the same

A semiconductor device includes an interface layer on a substrate, a gate dielectric layer on the interface layer, and a work function metal layer on the gate dielectric layer. An interface between the interface layer and the gate dielectric layer has a concentration of a dipole-inducing element. The semiconductor device also includes an oxygen blocking layer on the work function metal layer and a metal fill layer on the oxygen blocking layer.

Metal gates with layers for transistor threshold voltage tuning and methods of forming the same

A semiconductor device and related method for forming a gate structure. In some embodiments, a semiconductor device includes a fin extending from a substrate. In some cases, the fin includes a plurality of semiconductor channel layers. In some examples, the semiconductor device further includes a gate dielectric surrounding each of the plurality of semiconductor channel layers. In some embodiments, a first thickness of the gate dielectric disposed on a top surface of a topmost semiconductor channel layer of the plurality of semiconductor channel layers is greater than a second thickness of the gate dielectric disposed on a surface of another semiconductor channel layer disposed beneath the topmost semiconductor channel layer.

Gate structure for multi-gate device and related methods

A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.

Method for forming source/drain contacts

Growing community of inventors

Hsinchu County, Taiwan

Kuo-Feng Yu