Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo-Feng Yu

Jian-Hao Chen

Chun Hsiung Tsai

Shahaji B More

Chun-Hsiung Tsai

Cheng-Yi Peng

Shan-Mei Liao

Chia-Wei Chen

Kei-Wei Chen

Hui-Chi Chen

Yu-Ming Lin

Clement Hsingjen Wann

Yen-Ming Chen

Wen-Hung Huang

Yung-Hsiang Chan

Ziwei Fang

Shih-Chieh Chang

Shih-Hao Lin

Huai-Tei Yang

Shih-Hang Chiu

Chih-Yu Hsu

Feng-Cheng Yang

Kuei-Lun Lin

Shu-Wei Chung

Jian-Hsing Lee

Ming-Hsi Yeh

Da-Wen Lin

Chih-Wei Lee

Shyue-Shyh Lin

Chia-Yu Lu

Da-Yuan Lee

Chien-Tai Chan

Wei-Cheng Wang

Hsin-Han Tsai

Yen-Ju Chen

Wei Cheng Hsu

Wei-Yang Lee

Chih-Hsin Ko

Tung-Heng Hsieh

Chien-Hao Chen

Chung-Chiang Wu

Hsien-Ming Lee

Chandrashekhar Prakash Savant

Chia-Ching Lee

Hung-Chin Chung

Ya-Yun Cheng

Yin-Pin Wang

Chin-Shan Hou

Tsung-Ta Tang

Yu-Chia Liang

Cheng Hong Yang

An-Hung Tai

Mei-Yun Wang

Jaw-Juinn Horng

Chung-Hui Chen

Chia-Pin Lin

Chang-Yun Chang

King-Yuen Wong

Jiaw-Ren Shih

Chien-Yuan Chen

Chih-Hao Yu

Yi-Hsun Wu

Shu-Han Chen

Hsiu-Hao Tsao

Chih-Hung Wang

Zoe Chen

Chun-Chih Cheng

Hsueh-Ju Chen

Fu Chin Yang

Yao-Teng Chuang

Chang-Jhih Syu

Yi-Cheng Tsai

Dun-Nian Yaung

Chi On Chui

Yi-Tang Lin

Xiong-Fei Yu

Ming-Hsiang Song

Shao-Chang Huang

Ming-Te Chen

Kuan-Ting Liu

Hsien-Chin Lin

Tong-Chern Ong

Cheng-Hao Hou

Ming-Chi Huang

Juing-Yi Wu

Jun He

Jer-Fu Wang

Yuh-Ta Fan

Shu-Chuan Lee

Hoong Shing Wong

Chi-Sheng Lai

Tsung-Da Lin

Jo-Chun Hung

Yu-Jiun Peng

Wei-Chen Hsiao

Yu-jiun Peng

Hui-Ting Tsai

Chong-Gim Gan

Yen-Ta Lin

A method includes providing a structure having a first stack of nanostructures spaced vertically one from another and a second stack of nanostructures spaced vertically one from another, forming a dielectric layer wrapping around each of the nanostructures in the first and second stacks, depositing an n-type work function layer on the dielectric layer and a p-type work function layer on the n-type work function layer and over the first and second stacks. The n-type work function layer wraps around each of the nanostructures in the first stack. The p-type work function layer wraps around each of the nanostructures in the second stack. The method also includes forming an electrode layer on the p-type work function layer and over the first and second stacks.

Metal gates for multi-gate semiconductor devices and method thereof

In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

Method of manufacturing a semiconductor device

A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.

Methods for doping high-K metal gates for tuning threshold voltages

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece comprising a first channel member directly over a first region of a substrate and a second channel member directly over the first channel member, the first channel member being vertically spaced apart from the second channel member, conformally forming a dielectric layer over the workpiece, conformally depositing a dipole material layer over the dielectric layer, after the depositing of the dipole material layer, performing a thermal treatment process to the workpiece, after the performing of the thermal treatment process, selectively removing the dipole material layer, and forming a gate electrode layer over the dielectric layer.

P-type semiconductor devices with different threshold voltages and methods of forming the same

In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

Structure having gate spacers with projecting portions extending into a gate dielectric

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

Post gate dielectric processing for semiconductor device fabrication

In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode formed over a channel region, a first gate dielectric layer is formed over the channel region in the gate space, a second gate dielectric layer is formed over the first gate dielectric layer, one or more conductive layers is formed on the second gate dielectric layer, the second gate dielectric layer and the one or more conductive layers are recessed, an annealing operation is performed to diffuse an element of the second gate dielectric layer into the first gate dielectric layer, and one or more metal layers are formed in the gate space.

Method of manufacturing semiconductor devices and semiconductor devices

A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.

Forming low-resistance capping layer over metal gate electrode

An n-type field effect transistor includes semiconductor channel members vertically stacked over a substrate, a gate dielectric layer wrapping around each of the semiconductor channel members, and a work function layer disposed over the gate dielectric layer. The work function layer wraps around each of the semiconductor channel members. The n-type field effect transistor also includes a WF isolation layer disposed over the WF layer and a gate metal fill layer disposed over the WF isolation layer. The WF isolation layer fills gaps between adjacent semiconductor channel members.

Metal gates for multi-gate devices and fabrication methods thereof

A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.

Device providing multiple threshold voltages and methods of making the same

A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.

Semiconductor device with non-conformal gate dielectric layers

A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.

Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same

A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Semiconductor device and method of manufacture

A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.

Semiconductor device structure and methods of forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a cap layer over the gate stack. The semiconductor device structure includes a protective layer over the cap layer, wherein a lower portion of the protective layer extends into the cap layer. The semiconductor device structure includes a contact structure passing through the protective layer and the cap layer.

Semiconductor device structure and method for forming the same

Growing community of inventors

Hsinchu County, Taiwan

Kuo-Feng Yu