Taiwan Semiconductor Manufacturing Comp. Ltd.

Parabellum Strategic Opportunities Fund LLC

Kuo-Chung Yee

Chen-Hua Douglas Yu

Ying-Hao Kuo

Chun-Hui Yu

Chun-Hao Tseng

Jui Hsieh Lai

Hao-Yi Tsai

Tin-Hao Kuo

Jeng-Nan Hung

Jui-Pin Hung

Wan-Yu Lee

Tien-Yu Huang

Chien-Hsun Lee

Chun Hui Yu

Chih-Hang Tung

Po-Fan Lin

Mirng-Ji Lii

Jiun Yi Wu

Der-Chyang Yeh

Kai-Chiang Wu

Ming-Da Cheng

Chuei-Tang Wang

Ching-Hua Hsieh

Wei-Hung Lin

Chung-Hao Tsai

Tsung-Ding Wang

Jeng-Shien Hsieh

Yi-Da Tsai

Wei-Heng Lin

Liang-Ju Yen

Chung-Shi Liu

Szu-Wei Lu

Ying-Ching Shih

Chih-Wei Wu

Yu-Chia Lai

Yu-Hung Lin

Shih-Wei Chen

Po-Yuan Teng

Shih-Peng Tai

Wei-Ming Wang

Hung-Yi Kuo

Hsiu-Jen Lin

Chih-Hua Chen

Cheng-Chieh Hsieh

Hsiao-Wen Lee

Yeong-Jyh Lin

Kazuaki Hashimoto

Yian-Liang Kuo

Chi-Hui Lai

Chia-Hung Liu

Ying-Cheng Tseng

Chia-Hsiang Lin

Lawrence Chiang Sheu

Yu-Hsiao Lin

A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, a semiconductor substrate disposed on the dielectric layer and including a via opening with a notch in proximity to the dielectric layer, a through substrate via (TSV) disposed in the via opening of the semiconductor substrate and extending into the dielectric layer to land on the conductive pad, and a dielectric liner disposed in the via opening of the semiconductor substrate and filling the notch to laterally separate the TSV from the semiconductor substrate. A surface of the dielectric liner facing the TSV is substantially leveled with an inner sidewall of the dielectric layer facing the TSV.

Semiconductor structure having through substrate via and manufacturing method thereof

A semiconductor device includes a first die including a patterned conductive pad, a second die stacked over and electrically coupled to the first die, a bonding dielectric layer between the first and second dies, and a through die via penetrating through the first die and passing through the patterned conductive pad and the bonding dielectric layer. The second die includes a conductive pad directly over the patterned conductive pad. The bonding dielectric layer bonds the patterned conductive pad to the conductive pad, and the through die via directly lands on the conductive pad.

Semiconductor device including through die via

A semiconductor structure includes system-on-integrated chips, a first redistribution circuit structure and first conductive terminals. The system-on-integrated chips each include a die stack having two or more than two tiers, and each tier includes at least one semiconductor die. The first redistribution circuit structure is located on and electrically connected to the system-on-integrated chips. The first conductive terminals are connected on the first redistribution circuit structure, where the first redistribution circuit structure is located between the system-on-integrated chips and the first conductive terminals.

Semiconductor structure and method manufacturing the same

A package structure includes a wafer-form semiconductor package and a thermal dissipating system. The wafer-form semiconductor package includes semiconductor dies electrically connected with each other. The thermal dissipating system is located on and thermally coupled to the wafer-form semiconductor package, where the thermal dissipating system has a hollow structure with a fluidic space, and the fluidic space includes a ceiling and a floor. The thermal dissipating system includes at least one inlet opening, at least one outlet opening and a plurality of first microstructures. The at least one inlet opening and the at least one outlet opening are spatially communicated with the fluidic space. The first microstructures are located on the floor, and at least one of the first microstructures is corresponding to the at least one outlet opening.

Package structure and manufacturing method thereof

A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The first die, the second die and the third die are molded in a molding compound. The first redistribution layer is disposed on the molding compound and is electrically connected to the first die, the second die and the third die. The antenna is located on the molding compound and electrically connected to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna. The conductive elements are connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound.

A semiconductor package and a manufacturing method thereof is provided. The semiconductor package includes a first semiconductor die, including a substrate and transistors formed at a front side of the substrate; a power distribution network, spreading at a back side of the substrate and penetrating through the substrate, to provide power and ground signals to the transistors; a dielectric material, laterally surrounding the first semiconductor die; and a second semiconductor die, having a central portion bonded with the first semiconductor die and a peripheral portion in contact with the dielectric material.

Semiconductor package and manufacturing method thereof

A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.

ChipletsD SoIC system integration and fabrication methods

In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads.

Semiconductor packages and methods of forming same

A package structure is provided. The package structure includes a die, an encapsulant and a RDL structure. The RDL structure is disposed on the die and the encapsulant. The RDL structure includes a first dielectric structure and a first redistribution layer. The first dielectric structure includes a first dielectric material layer and a second dielectric material layer on the first dielectric material layer. The first redistribution layer is embedded in the first dielectric structure and electrically connected to the die. The redistribution layer includes a first seed layer and a first conductive layer surrounded by the first seed layer. A topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer.

Package structure

A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.

Thermal structure for semiconductor device and method of forming the same

A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.

Semiconductor structure including thermal enhanced bonding structure

An integrated circuit structure and method of forming is provided. A die is placed on a substrate and encased in molding compound. A redistribution layer is formed overlying the die and the substrate is removed. One or more surface mounted devices and/or packages are connected to the redistribution layer on an opposite side of the redistribution layer from the die. The redistribution layer is connected to a printed circuit board.

Integrated circuit structure

A semiconductor package includes a first die, a first heat conduction block and a first encapsulant. The first die has a bottom surface, a top surface and a sidewall between the bottom surface and the top surface. The first heat conduction block has a bottom surface, a top surface and a sidewall between the bottom surface and the top surface. The first encapsulant is disposed between the sidewall of the first die and the sidewall of the first heat conduction block.

3D semiconductor packages

A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.

Packaged semiconductor device and method of forming thereof

Microelectromechanical systems (MEMS) packages and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a MEMS package may include attaching a MEMS structure having a capping structure thereon to a device wafer comprising a plurality of first devices formed therein to form a wafer level MEMS package; and singulating the device wafer having the MEMS structure attached thereto to form a plurality of chip scale MEMS packages.

MEMS packages and methods of manufacture thereof

Growing community of inventors

Taoyuan, Taiwan

Kuo-Chung Yee