Mediatek Corporation

Other

Taiwan Semiconductor Manufacturing Comp. Ltd.

National Yang Ming Chiao Tung University

Silicon Integrated Systems Corporation

Global Unichip Corporation

Admtek Incorporated

Kuo-Chun Hsu

Ming-Dou Ker

Wei-Chung Chen

Hsin-Chin Jiang

Chao-Chang Chiu

Chih-Wei Chang

Wen-Yu Lo

Tzu-Chi Huang

Chen Tsou

Chin-Hsiang Liang

Yan-Ting Liou

A current sensing circuit includes an inductor current sensing circuit and a processing circuit. The inductor current sensing circuit senses an inductor current of a direct current to direct current (DC-to-DC) converter to generate a first sensed current signal, wherein an average value of the first sensed current signal is not a constant under different input voltages of the DC-to-DC converter. The processing circuit generates a second sensed current signal, wherein the first sensed current signal is involved in generation of the second sensed current signal, the second sensed current signal is involved in current-mode control of the DC-to-DC converter, and an average value of the second sensed current signal is a constant under said different input voltages of the DC-to-DC converter.

Current sensing circuit for generating sensed current signal with average value being constant under different input voltages of direct current to direct current converter and associated current-mode control circuit

A switching regulator includes a first switch circuit, a second switch circuit, and a protection circuit. The first switch circuit has a first connection node coupled to a first reference voltage, and a second connection node coupled to one end of an inductor. The second switch circuit has a first connection node coupled to a second reference voltage, and a second connection node coupled to the one end of the inductor. The protection circuit senses a voltage level at the first connection node of the first switch circuit, and selectively enables an auxiliary current path in response to the voltage level at the first connection node of the first switch circuit, wherein the auxiliary current path and at least the first switch circuit are arranged in a parallel connection fashion.

Switching regulator using protection circuit for avoiding voltage stress and associated power management integrated circuit

The invention provides a method for improving efficiency of a power converter which may include a switch coupled between a power source and a middle node, and may supply an inductor current at the middle node to result in an output voltage and a load current. The method may comprise: during an intermediate mode, controlling the inductor current to ripple with peaks at a peak current threshold and valleys which may vary as the load current varies.

Method for improving efficiency of power converter

Voltage regulators and related methods are described. The voltage regulators described in the application may include an operational amplifier, an output transistor, and a signal buffer connected between the operational amplifier and the output transistor. In some embodiments, these voltage regulators are used in connection with memory units. A voltage regulator may be arranged such that the signal amplifier clamps the voltage at the gate of the output transistor to the output voltage when the memory unit is in an idle mode. In this way, when the memory is accessed, the amplitude and duration of output voltage overshoots can be limited, relative to some voltage regulators.

Systems for voltage regulation using signal buffers and related methods

An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.

Electrostatic discharge protection device for mixed voltage interface

A clock generator includes a current source for generating a constant current; a current mirror coupled between a supply voltage and the current source for generating a mirror current equal to the constant current multiplied by a predetermined value; and a charge control module coupled with the current source and the current mirror for charging a capacitor when a voltage thereof is lower than a predetermined threshold voltage and for discharging the capacitor when the voltage thereof is higher than the predetermined threshold voltage, thereby generating a clock signal at a predetermined frequency, wherein the charge control module adjusts the predetermined frequency by changing the predetermined threshold voltage.

Clock generator with reduced electromagnetic interference for DC-DC converters

An ESD protection circuit using a double-triggered silicon controller rectifier (SCR). The double-triggered silicon controller rectifier (SCR) includes N+ diffusion areas, P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.

Electrostatic discharge protection circuit using a double-triggered silicon controlling rectifier

A double-triggered silicon controller rectifier (SCR) comprises a plurality of N+ diffusion areas, a plurality of P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.

Double-triggered silicon controlling rectifier and electrostatic discharge protection circuit thereof

A power-rail ESD clamp circuit for mixed-voltage I/O buffer is proposed. The power-rail ESD clamp circuit comprises an ESD detection circuit and an ESD protection device. Under normal operating condition, the ESD detection circuit will not trigger the ESD protection device, and therefore the component used in the circuit will not have the gate-oxide reliability issue and also will not generate undesirable leakage current. Under ESD-zapping conditions, the ESD detection circuit will provide some trigger voltage or current to bias the ESD protection device. The ESD protection device can be triggered on quickly to discharge the ESD energy efficiently.

Power-rail ESD clamp circuit for mixed-voltage I/O buffer

An ESD protection circuit with high substrate-triggering efficiency. The circuit comprises a multi-finger-type device having a plurality of finger gates below which a parasitic BJT is formed, a plurality of finger sources, each of which is an emitter of one parasitic BJT, and at least one finger drain coupled to a pad, a plurality of voltage drop elements, each of which is coupled between one of the finger sources and a power line to detect a transient current flowing through one of the finger gates, and a plurality of feedback circuits, each of which is coupled between a base and an emitter respectively of a first and second parasitic BJT, and activates the first BJT to bypass ESD current during an ESD event.

ESD protection circuit with high substrate-triggering efficiency

An electrostatic discharge protection circuit. The electrostatic discharge protection circuit utilizes the non-uniform triggering of multi-finger gate-grounded NMOS. The source of the finger which has the potential to trigger on is coupled to the base terminal of all the parasitic bipolar transistor of all the other multi-finger gate-ground NMOS structures. Thus, the finger which has the potential to be triggered can be used as a triggering device to trigger the other finger devices during an ESD event. By using this method, the ESD protection NMOS or PMOS, realized with multi-finger layout structure, can be uniformally triggered on to discharge ESD current. Therefore, it can have a high ESD robustness in a small layout area.

Growing community of inventors

Hsinchu, Taiwan

Kuo-Chun Hsu