Springsoft, Inc.

Synopsys, Inc.

Springsoft Usa, Inc.

Kuo-Ching Lin

Kai Yang

Michael Lyons

Jean-Marc Albert Forey

Nan-Ting Yeh

Wei-Ting Tu

Kuen-Yang Tsai

Chih-Wen Chang

Tien-Chun Wei

Tein-Chun Wei

Ranking of fault-test pairs is performed using first and second multitudes of waveform statistics. The first multitude of waveform statistics includes first value-change information regarding variations in logics HIGH and LOW for each bit of each reference output resulting from a test run of the design code. The second multitude of waveform statistics includes second value-change information regarding variations in logics HIGH and LOW for each bit of each faulty output resulting from a test run of the design code injected with a fault. Relative differences between the first and second multitudes of waveform statistics for each bit of each faulty output with respect to the corresponding reference output are determined. A waveform difference based on the relative differences for each signal of each faulty output is determined. A ranking result of fault-test pairs is determined according to the waveform differences of the faulty outputs.

Method for ranking fault-test pairs based on waveform statistics in a mutation-based test program evaluation system

Methods and systems for evaluating checker quality of a verification environment are provided. In some embodiments, an overall sensitivity for the verification environment and an individual sensitivity for a respective checker are calculated. The overall sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to a checker system including at least one checker, can be detected by the verification environment. The individual sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to at least one specific probe among a plurality of probes of a design, can be detected by the checker corresponding to the specific probe. The overall checker sensitivity numbers can show the robustness of the check system. The individual checker sensitivity can guide the user which individual checker or checkers to improve.

Methods and systems for evaluating checker quality of a verification environment

A computer-based simulation process executes a checkpoint operation while simulating behavior of an electronic circuit by forking an active checkpoint process having the same state as the original simulation process. While simulation time for the simulation process continues to increase after executing the checkpoint operation, simulation time for the checkpoint process remains unchanged so that the checkpoint process remains in the state of the simulation at the simulation time it executed the checkpoint operation (the 'checkpoint time'). When the checkpoint process subsequently receives a request to resume simulating the circuit, it forks a new simulation process that mimics the original simulation process as of checkpoint time, and the new simulation process then begins to advance its simulation time, thereby enabling it to re-simulate behavior of the electronic circuit previously simulated by the original simulation process starting from the checkpoint time.

HDL re-simulation from checkpoints

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Taichung, Taiwan

Kuo-Ching Lin