Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo Ching Huang

Tse-Liang Ying

Cheng-Ming Wu

Mong-Song Liang

Wen-Chuan Chiang

Yean-Kuen Fang

Dun-Nian Yaung

Yu-Hua Lee

Cheng-Yeh Shih

Yu Hua Lee

Jhon-Jhy Liaw

Cheng Yeh Shih

Dun Nian Yaung

Chia-Shiung Tsai

Chen-Jong Wang

Shou-Gwo Wuu

Jenn Ming Huang

Li-Chih Chao

James Cheng-Ming Wu

James (Cheng-Ming) Wu

Ming-Hsin Li

A method using a single masking step for making double-cylinder stacked capacitors for DRAMs which increases capacitance while eliminating erosion of an underlying oxide insulating layer when the masking step is misaligned is described. A planar silicon oxide (SiO ) first insulating layer is formed over device areas, and a first silicon nitride (Si N ) etch-stop layer is deposited, and openings are etched for capacitor node contacts. A first polysilicon layer is deposited to a thickness sufficient to fill the openings and to form an essentially planar surface. A second insulating layer is deposited and patterned to form portions with vertical sidewalls over the node contacts. A conformal second Si N layer is deposited and etched back to form spacers on the vertical sidewalls, and the first polysilicon layer is etched to the first Si N layer. The second insulating layer is selectively removed using HF acid while the first polysilicon and first Si N layers prevent etching of the underlying first SiO layer. A second polysilicon layer is deposited and etched back to form double-cylinder sidewalls for the capacitor bottom electrodes. The first and second Si N layers are removed in hot phosphoric acid. The capacitors are completed by forming an interelectrode dielectric layer on the bottom electrodes, and depositing a third polysilicon layer for top electrodes.

Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM)

This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second poly-silicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate. Fuse windows (openings) are then selectively etched in the ILD layers to the etch-stop layer and the etch-stop layer is selectively etched in the fuse window to the insulating layer over the fuse area. This process allows fuse structures to be built without overetching that can cause fuse damage. The uniform thick insulating layer allows repeatable and reliable laser abrading (evaporation) to open the desired fuses.

Method for making a fuse structure for improved repaired yields on semiconductor memory devices

The invention provides a method for fabricating a shallow trench isolation which is not susceptable to buried contact trench formation. The invention also provides immunity from the STI &ldquo;kink effect,&rdquo; as well as benefits associated with nitridation. The process begins by forming a pad oxide layer on a semiconductor substrate. A nitride layer is formed on the pad oxide layer. The nitride layer, the pad oxide layer, and the semiconductor substrate are patterned to form trenches. Next, a fill oxide layer is formed over the nitride layer, the pad oxide layer, and the semiconductor substrate. The fill oxide layer is chemical-mechanical polished, stopping on the nitride layer to form fill oxide regions. N,ions are implanted into the fill oxide regions. An anneal is performed to form a buried oxynitride layer. The buried oxynitride layer is partially above the level of the top surface of the semiconductor substrate and partially below the level of the top surface of the semiconductor substrate. The nitride layer is removed. Then, the pad oxide layer and portions of the fill oxide regions are removed using the buried oxynitride layer as an etch stop, forming shallow trench isolations.

Method for fabricating a shallow trench isolation which is not susceptible to buried contact trench formation

A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

Trench-free buried contact

A method was achieved for making improved self-aligned contacts (SAC) to a patterned polysilicon layer, such as gate electrodes for FETs. Lightly doped source/drain areas are implanted. A second insulating layer is deposited and etched back to form first sidewall spacers. A silicon nitride etch-stop layer and a first interpolysilicon oxide (IPO1) layer are deposited. First SAC openings are etched in the IPO1 layer to the etch-stop layer, and concurrently openings are etched for the gate electrodes, eliminating a masking step. The etch-stop layer is etched in the SAC openings to form second sidewall spacers that protect the first sidewall spacers during BOE cleaning of the contacts. A patterned polycide layer is used to make SACs and electrical interconnections. A second IPO layer is deposited to provide insulation, and an interlevel dielectric layer is deposited. Second SAC openings are etched to the etch-stop layer for the next level of metal interconnections, while the contact openings to the gate electrodes are etched to completion. The etch-stop layer is etched in the second SAC openings to form second sidewall spacers to protect the first sidewall spacers during cleaning. Metal plugs are formed from a first metal in the second SAC openings and in the openings to the gate electrodes. A second metal is patterned to complete the structure to the first level of metal interconnections.

Double spacer technology for making self-aligned contacts (SAC) on

A method of forming a grooved fuse (plug fuse) in the same step that via plugs are formed in the guard ring area 14 and in product device areas. A key point of the invention is to form fuses from the via plug layer, not from the metal layers. Also, key guard rings are formed around the plug guise. The invention can include the following: a semiconductor structure is provided having a fuse area, a guard ring area surrounding the fuse area; and a device area. First and second conductive strips are formed. First and second insulating layers are formed over the first and second conductive strips. Plug contacts and fuse plugs are formed through the first and second insulating layers to the first and second conductive strips. A third insulating layer is formed over the second insulating layer. Metal lines are formed over the third insulating layer in the device area. A fuse via opening is formed in the third insulating layer. A plug fuse is formed in the fuse via opening. A fourth insulating layer is formed over the plug fuse and the third insulating layer. A fuse opening is formed at least partially though the fourth insulating layer over the fuse area.

Method for forming a fuse in integrated circuit application

This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second polysilicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate. Fuse windows (openings) are then selectively etched in the ILD layers to the etch-stop layer and the etch-stop layer is selectively etched in the fuse window to the insulating layer over the fuse area. This process allows fuse structures to be built without overetching that can cause fuse damage. The uniform thick insulating layer allows repeatable and reliable laser abrading (evaporation) to open the desired fuses.

Method for making a fuse structure for improved repaired yields on

A method of forming a deep contact by forming a dielectric layer 20 over a semiconductor structure 10. A main point is that the hard mask 30 is removed after the plug 52 is formed. A hard mask layer 30 is formed over the dielectric layer 20. A contact photoresist layer 36 is formed over the hard mask layer 30. The hard mask layer 30 is etched through the contact photoresist opening 39 to form a contact hard mask opening 41 exposing the dielectric layer 20. The dielectric layer 20 is etched using a high density plasma etch process using the contact photoresist layer 36 and the hard mask layer 30 as an etch mask forming a contact hole 40 in the dielectric layer 20. The contact photoresist layer 36 is removed. A metal layer 50 is formed filling the contact hole 40 and covering over the hard mask layer 30. The metal layer 50 is etched back forming a plug 52 filling the contact hole 40. Now, the hard mask layer 30 is removed. The removal of the hard mask 30 after the metal layer 50 deposition: (a) prevents the contact hole 40 from being contaminated from photoresist and other contamination formed during the hard mask 30 removal steps; and (b) creates a plug 52 that does not have a recess.

Method to form a recess free deep contact

A new method of forming a buried contact junction in a process involving shallow trench isolation is described. A first silicon oxide layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. An opening is etched in the first silicon nitride and pad oxide layers where they are not covered by a mask. The substrate underlying the opening is etched into to form a shallow trench. An oxide material is deposited over the surface of the first silicon nitride layer and within the shallow trench and planarized to the surface of the first silicon nitride layer wherein the oxide material forms a STI region. The first silicon nitride layer is removed whereby the STI protrudes above the pad oxide layer. The pad oxide layer is removed whereby the corners of the STI above the substrate are also removed. A second silicon nitride layer is deposited overlying a sacrificial oxide layer and etched away to leave silicon nitride spacers filling in and rounding the corners of the STI. The sacrificial oxide layer is removed. A gate electrode and source/drain regions are formed in and on the substrate wherein a source/drain is adjacent to the STI. The gate electrode and STI are covered with an insulating layer. An opening is etched through the insulating layer to the source/drain region wherein the silicon nitride spacer at the corner of the STI prevents etching of the STI. The opening is filled with a conducting layer to complete formation of a contact.

Method to form trench-free buried contact in process with STI technology

Process to form a trench-free buried contact

A process for creating an insulator filled, shallow trench, in a semiconductor substrate, in which the insulator layer in the shallow trench, is not exposed to procedures used to remove defining composite insulator layers, has been developed. The process features creating a lateral recess, in a thick silicon nitride layer, used as a component of a composite insulator layer, where the composite insulator layer is used for subsequent definition of the shallow trench, in the semiconductor substrate. An insulator deposition, filling openings, and recesses, in the composite insulator layer, and filling the shallow trench, followed by removal of excess insulator fill, on the top surface of the composite insulator layer, results in the formation of a 'T' shape insulator, comprised of an insulator shape, in the shallow trench, and comprised of a wider insulator shape, located in the composite insulator shape, with the lateral recess in the thick silicon nitride layer, and with the wider insulator shape, overlying the narrow, insulator shape, in the shallow trench. The insulator, in the shallow trench, is protected from the procedure used to remove components of the composite insulator layer, by the wider insulator shape.

Shallow trench isolation technology to eliminate a kink effect

A contact between a conductor and a substrate region in a MOSFET SRAM device is formed by a dielectric layer on the surface of a partially completed SRAM device with pass transistors and latch transistors with the dielectric layer being formed above those pass and latch transistors. A thin film transistor gate electrode and an interconnection line are formed on the upper surface of the dielectric layer. A gate oxide layer covers the gate electrode and the interconnection line. A polysilicon conductive layer which covers the gate oxide layer includes a channel region between a source region and a drain region which are formed on opposite sides of the channel region. There is a channel mask formed self-aligned with the channel region formed above the channel region as well as being above the gate electrode. The polysilicon conductive layer is doped aside from the channel mask thereby providing a source region and a drain region on opposite sides of the channel region. A doped interconnect line is also formed in the polysilicon conductive layer. There is a contact which extends through the gate oxide layer between the interconnection line and the polysilicon conductive layer.

SRAM memory device with improved performance

A method of manufacturing a memory device having embedded logic. The memory and logic FETS have two different two gate oxide 20 34 thicknesses. The method integrates (1) a salicide contact process 72 74 (logic devices) and dual gate (N+/P+) logic gate 24A 24B technology with (2) memory device Polycide with Self aligned Contact 80 Technology. The method comprises:

Method for fabricating a dual-gate dielectric module for memory embedded

A method for increasing the surface area, and thus the capacitance of a DRAM, stacked capacitor structure, has been developed. A storage node electrode, incorporating branches of polysilicon, is created via use of multiple polysilicon and insulator depositions, as well as via the use of dry anisotropic, and wet isotropic, etching procedures. The use of polysilicon spacers, created on the sides of silicon oxide mesas, adds a vertical component to the polysilicon branches. Removal of a portion of insulator layer from between polysilicon branches, results in exposure of the increased storage node electrode surface area. Unetched portions of the insulator layers, between polysilicon branches, supply structural support for the storage node electrode, comprised of polysilicon branches.

Capacitor structure for a dynamic random access memory cell

A new method for forming stacked capacitors for DRAMs having improved yields when the bottom electrode is misaligned to the node contact is achieved. A planar silicon oxide (SiO.sub.2) first insulating layer, a Si.sub.3 N.sub.4 etch-stop layer, and a disposable second insulating layer are deposited. First openings for node contacts are etched in the insulating layers. A polysilicon layer is deposited and etched back to form node contacts in the first openings. The node contacts are recessed in the second insulating layer, but above the etch-stop layer to form node contacts abutting the etch-stop layer. A disposable third SiO.sub.2 layer is deposited. Second openings for bottom electrodes are etched over and to the node contacts. A conformal second polysilicon layer is deposited and chem/mech polished back to form the bottom electrodes in the second openings. The third and second insulating layers are removed by wet etching to the etch-stop layer. When the second openings are misaligned over the node contact openings, the polysilicon plugs abutting the Si.sub.3 N.sub.4 etch-stop layer protect the SiO.sub.2 first insulating layer from being eroded over the devices on the substrate. The capacitors are completed by forming a thin dielectric layer on the bottom electrodes, and forming top electrodes from a patterned third polysilicon layer.

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Kaohsiung, Taiwan

Kuo Ching Huang