Taiwan Semiconductor Manufacturing Comp. Ltd.

National Science Council of Republic of China

Kuo-Ching Huang

Yu-Wei Ting

Chun-Yang Tsai

Chao-Yang Chen

Cheng-Jun Wu

Yi Ching Ong

Wen-Ting Chu

Wen-Chuan Chiang

Tse-Liang Ying

Kuo-Pin Chang

Dun-Nian Yaung

Kuen-Yi Chen

Kuo-Chi Tu

Harry-Hak-Lay Chuang

Wen-Cheng Chen

Yi-Hsuan Chen

Pili Huang

Hung-Ju Li

Shou-Gwo Wuu

Kuo-Chyuan Tzeng

Yean-Kuen Fang

Tong-Chern Ong

Wei Ting Hsieh

Jin-Yuan Lee

Chi-Wen Liu

Chen-Jong Wang

Chih-Yang Chang

Chung-Wei Chang

Jenn-Ming Huang

Tsung-Hao Yeh

Mickey Hsieh

Wei-Cheng Wu

Mong-Song Liang

Tien-Lu Lin

Chia-Fu Lee

Chung-Cheng Wu

Hsiao-Hui Tseng

Yu-Hua Lee

Min-Hsiung Chiang

Henry Wang

Chun-Yao Chen

Chien Hung Liu

Ho-Ching Chien

Hon-Jarn Lin

Chih-Yang Pai

Tsung-Hsun Huang

Huey-Chi Chu

Hsin Fu Lin

Kuei-Ying Lee

Jin Yuan Lee

Ji-Chung Huang

Jang-Cheng Hsieh

Kuo-pin Chang

Jian-Yu Shen

Fu-Hai Li

Chin-Yang Chang

Chien Ta Huang

Hsien Jung Chen

Ching-En Chen

Chung-Yao Chen

Chuan-Jane Chao

Kuo-Chuang Tseng

A device structure includes a voltage regulator circuit, which includes: a first semiconductor die including a pulse width modulation (PWM) circuit and connected to a PWM voltage output node at which a pulsed voltage output is generated; and a series connection of an inductor and a parallel connection circuit, the parallel connection circuit including a parallel connection of capacitor-switch assemblies. A first end node of the series connection is connected to the PWM voltage output node; a second end node of the series connection is connected to electrical ground; each of the capacitor-switch assemblies includes a respective series connection of a respective capacitor and a respective switch; and each switch within the capacitor-switch assemblies is located within the first semiconductor die.

Voltage regulator having variable output capacitance and methods for forming the same

Some embodiments relate to a method of forming a redistribution layer (RDL) stack of a 3D integrated circuit stack. The method comprises removing a substrate form the first side of a first die to expose a first dielectric layer. A spiral trench is formed in the first dielectric layer with one end of the spiral trench directly over a through silicon via (TSV) beneath the first dielectric layer. A first barrier layer is formed along sidewalls of the spiral trench, the first barrier layer being thermally coupled to the TSV. A first conductive wire is formed within the spiral trench, separated from the first dielectric layer by the barrier layer.

Techniques for heat dispersion in 3D integrated circuit

A semiconductor structure may be located over a substrate, and may include a parallel connection of a first component and a second component. The first component includes a series connection of a diode and a capacitor that is selected from a metal-ferroelectric-metal capacitor and a metal-antiferroelectric-metal capacitor. The second component includes a battery structure. The semiconductor structure may be used as a combination of an energy harvesting device and an energy storage structure that utilizes heat from adjacent semiconductor devices or from other heat sources.

Energy harvest and storage device for semiconductor chips and methods for forming the same

A device structure includes a first series connection of a first phase change memory (PCM) switch and a second PCM switch. The first PCM switch includes a first heater line, a first PCM line, and a first contact electrode and a second contact electrode located on the first heater line. The second PCM switch includes a second heater line, a second PCM line, and a third contact electrode and a fourth contact electrode located on the second heater line. The second contact electrode is electrically connected to the third contact electrode. The fourth contact electrode is electrically grounded. One of the first contact electrode and the second contact electrode includes an radio-frequency (RF) signal input port. Another of the first contact electrode and the second contact electrode comprises an RF signal output port. The device structure may function as a combination PCM switch that decreases noise level during signal transmission.

Phase change material switch circuit for enhanced signal isolation and methods of forming the same

One embodiment of the present disclosure provides an optical device which includes a waveguide and a light modulator. The light modulator comprising a bridge segment positioned on the waveguide, wherein the bridge segment comprises a phase-change material. The optical device also includes a heating member. The heating member includes an intermediate segment and two electric contact segments. The intermediate segment is in direct contact with the bridge segment of the light modulator. The two electric contact segments are connected to two ends of the intermediate segment, wherein heat produced from the heating member is directly transferred to the bridge segment of the light modulator thereby inducing a phase transition thereof.

Optical device with phase-change materials and method of fabricating the same

A semiconductor device includes a first capacitor having a ferroelectric film disposed between two electrodes, a second capacitor, having another dielectric film disposed between two electrodes. A first voltage is applied across the first capacitor such that the ferroelectric film is polarized, altering the effective resistance through the device. A second voltage is applied across the first capacitor, such that a leakage current transits the ferroelectric film, and accumulates along an electrode of the second capacitor, and the gate of a transistor, thereby effecting a change to the drain to source resistance of the transistor which may be measured to determine the polarization state of the ferroelectric film.

Ferroelectric tunnel junction memory devices with enhanced read window

A cell array of a memory device includes: a first deck of memory cells arranged in a first row and a second row extending in a first horizontal direction and a plurality of columns extending in a second horizontal direction, wherein the memory cells in the second row in the first deck is displaced in the first horizontal direction with respect to the memory cells in the first row in the first deck; a first common word line metal track extending in the first horizontal direction, wherein both the memory cells in the first row and the memory cells in the second row are disposed on the first common word line metal track; and a plurality of first bit line metal tracks extending in the second horizontal direction, wherein each of the plurality of first bit line metal tracks is disposed on one of the first deck of memory cells.

Cross-point architecture for PCRAM

A semiconductor device includes a ferroelectric tunnel junction (FTJ), wherein the ferroelectric tunnel junction includes a first electrode, a ferroelectric layer disposed over the first electrode, and a second electrode disposed over the ferroelectric layer. The first electrode contains nitrogen or oxygen and is characterized by a first percentage of nitrogen or oxygen. The second electrode contains nitrogen or oxygen and is characterized by a second percentage of nitrogen or oxygen. The first percentage is different from the second percentage.

Ferroelectric tunnel junctions with conductive electrodes having asymmetric nitrogen or oxygen profiles

Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.

High electron affinity dielectric layer to improve cycling

A one-time programmable (OTP) memory includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, each memory cell of the plurality of memory cells including a first terminal coupled to a bit line of the plurality of bit lines, a second terminal coupled to a word line of the plurality of word lines, and a selector coupled between the first terminal and the second terminal and having a threshold voltage that is alterable by an electric current.

One-time programmable (OTP) memory and method of operating the same

The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.

Integrated chip with solid-state power storage device

Phase change material (PCM) switches and methods of fabrication thereof that provide improved thermal confinement within a phase change material layer. A PCM switch may include a dielectric capping layer between a heater pad and the phase change material layer of the PCM switch that is laterally-confined such opposing sides of the dielectric capping layer the heater pad may form continuous surfaces extending transverse to the signal transmission pathway across the PCM switch. Heat transfer from the heater pad through the dielectric capping layer to the phase change material layer may be predominantly vertical, with minimal thermal dissipation along a lateral direction. The localized heating of the phase change material may improve the efficiency of the PCM switch enabling lower bias voltages, minimize the formation of regions of intermediate resistivity in the PCM switch, and improve the parasitic capacitance characteristics of the PCM switch.

Phase change material switch with improved thermal confinement and methods for forming the same

A memory device is provided in various embodiments. The memory device, in those embodiments, has an ovonic threshold switching (OTS) selector comprising multiple layers of OTS materials to achieve a low leakage current and as well as relatively low threshold voltage for the OTS selector. The multiple layers can have at least one layer of low bandgap OTS material and at least one layer of high bandgap OTS material.

Selector for memory device

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a heater element on the semiconductor substrate, the heater element configured to generate heat in response to a current flowing therethrough. The semiconductor device also includes a conductor material having a programmable conductivity, and an insulator layer between the heater element and the conductor material, where the conductor material is configured to be programmed by applying one or more voltage differences to one or more of the heater element and the conductor material, and where a capacitance between the conductor material and the heater element is configured to be controlled by the voltage differences such that the capacitance is lower while the conductor material is being programmed than while the conductor material is not being programmed.

Heat controlled switch

A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.

Memory device structure and manufacturing method thereof

Growing community of inventors

Hsinchu, Taiwan

Kuo-Ching Huang