United Microelectronics Corp.

Kuo-Chin Hung

Wei-Chuan Tsai

Min-Chuan Tsai

Chun-Tsen Lu

Chi-Mao Hsu

Kuo-Chih Lai

Hsin-Fu Huang

Kun-Ju Li

Pin-Hong Chen

YI-Fan Li

Chun-Chieh Chiu

Fu-Shou Tsai

Ti-Bin Chen

Wen-Yi Teng

Li-Han Chen

Chia-Chang Hsu

Li-Chieh Hsu

Yi-Han Liao

Po-Cheng Huang

Yu-Ting Li

Wen-Chin Lin

Yen-Tsai Yi

Jui-Ming Yang

Huan-Chi Ma

Wu-Sian Sie

Chien-Wen Yu

Kuan-Chun Lin

Shao-Ping Chen

Chun-Lin Chen

Kun Ju Li

Hsin Jung Liu

Yi Han Liao

A first gate and a second gate are formed on a substrate with a gap between the first and second gates. The first gate has a first sidewall. The second gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.

Method for fabricating semiconductor structure

A first dummy gate and a second dummy gate are formed on a substrate with a gap between the first and second dummy gates. The first dummy gate has a first sidewall. The second dummy gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second dummy gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.

A semiconductor structure is disclosed. The semiconductor structure includes first and second metal gates on a substrate with a gap therebetween. The first metal gate has a first sidewall, and the second metal gate has a second sidewall directly facing the first sidewall. A contact etch stop layer (CESL) is disposed within the gap and extends along the first and second sidewalls. The CESL has a first top portion adjacent to a top surface of the first metal gate and a second top portion adjacent to a top surface of the second metal gate. The first top portion and the second top portion have a trapezoid cross-sectional profile. A first sidewall spacer is disposed on the first sidewall and between the CESL and the first metal gate. A second sidewall spacer is disposed on the second sidewall and between the CESL and the second metal gate.

Semiconductor structure and method for fabricating the same

A method for forming a semiconductor device is disclosed. A p-type field-effect transistor (p-FET) is formed on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate and completely covers the p-FET. At least an opening is formed in the dielectric layer and exposes a source/drain region of the p-FET. A conductive material is then formed filling the opening, wherein the conductive material comprises a first stress; specifically, a tensile stress between 400 and 800 MPa.

Semiconductor device and method of forming the same

A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.

Conductive layout structure including high resistive layer

A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

Semiconductor process

A conductive structure includes a substrate including a first dielectric layer formed thereon, a first trench formed in the first dielectric layer, a first barrier layer formed in the first trench, a first nucleation layer formed on the first barrier layer, a first metal layer formed on the first nucleation layer, and a first high resistive layer sandwiched in between the first barrier layer and the first metal layer.

Conductive structure having an entrenched high resistive layer

A semiconductor structure includes a substrate having thereon a dielectric layer. An opening is formed in the dielectric layer. The opening includes a bottom surface and a sidewall surface. A diffusion barrier layer is conformally disposed along the sidewall surface and the bottom surface of the opening. A nucleation metal layer is conformally disposed on the diffusion barrier layer. A bulk metal layer is disposed on the nucleation metal layer. A film-growth retarding layer is disposed between the nucleation metal layer and the bulk metal layer.

Semiconductor structure and fabrication method thereof

Semiconductor process and semiconductor device

A method of manufacturing a semiconductor structure, comprising: providing a preliminary structure having a first region and a second region and comprising a plurality of first trenches in the first region; forming a metal layer filling the first trenches covering on the preliminary structure, wherein the metal layer comprises a concave portion in the second region and the concave portion defines an opening; forming a metal nitride layer on the metal layer by an nitride treatment; and performing a planarization process to remove the metal nitride layer and a portion of the metal layer to expose the preliminary structure.

Fabricating method of semiconductor structure

The present invention utilizes a barrier layer in the contact hole to react with an S/D region to form a silicide layer. After forming the silicide layer, a directional deposition process is performed to form a first metal layer primarily on the barrier layer at the bottom of the contact hole, so that very little or even no first metal layer is disposed on the barrier layer at the sidewall of the contact hole. Then, the second metal layer is deposited from bottom to top in the contact hole as the deposition rate of the second metal layer on the barrier layer is slower than the deposition rate of the second metal layer on the first metal layer.

Semiconductor device with a contact plug and method of fabricating the same

A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural trenches, and the adjacent trenches are spaced apart from each other. A barrier layer is formed on an upper surface of the insulation and in sidewalls of the trenches, and the barrier layer comprises overhung portions corresponding to the trenches. A seed layer is formed on the barrier layer. Then, an upper portion of the seed layer formed on an upper surface of the barrier layer is removed. An upper portion of the barrier layer is removed for exposing the upper surface of the insulation. Afterwards, the conductors are deposited along the seed layer for filling up the trenches, wherein the top surfaces of the conductors are substantially aligned with the upper surface of the insulation.

Method for manufacturing semiconductor device with a barrier layer having overhung portions

Growing community of inventors

Changhua County, Taiwan

Kuo-Chin Hung