United Microelectronics Corp.

Kuo-Chih Lai

Nien-Ting Ho

Chi-Mao Hsu

Shih-Min Chou

Chia-Chang Hsu

Wei-Ming Hsiao

Yen-Chen Chen

Hsin-Fu Huang

Yang-Ju Lu

Yi-Wei Chen

Pin-Hong Chen

Li-Han Chen

Chia Chang Hsu

Bor-Shyang Liao

Shu Min Huang

Min-Chuan Tsai

Yun-Tzu Chang

Ching-Yun Chang

Chun-Chieh Chiu

Min-Chung Cheng

Chin-Fu Lin

Chien-Chung Huang

Chun-Yao Yang

Wei Chen

Wei-Chuan Tsai

Chun-Ling Lin

Ko-Wei Lin

Shu-Min Huang

Szu-Yao Yu

Teng-Chun Tsai

Yu-Tsung Lai

Mei-Ling Chen

Kuo-Chin Hung

Yi-Syun Chou

Hsiang-Chieh Yen

Wei-Ning Chen

Chia-Fu Cheng

Yu-Ru Yang

Su-Jen Sung

Kuan-Chun Lin

Hui-Ting Lin

Pei-Hsun Kao

Hui-Lin Wang

Bin-Siang Tsai

Chun-Yuan Wu

Chung-Yi Chiu

An-Chi Liu

Yu-Shu Lin

Po-Cheng Huang

Chao-Ching Hsieh

Yu-Wen Wang

Jei-Ming Chen

Ai-Sen Liu

Ching-I Li

Chun-Jen Huang

Yen-Tsai Yi

Tsung-Hsun Tsai

Hsin-Chih Yu

Ya-Jyuan Hung

Jen-Po Huang

Ming-Chang Lu

Miao-Chun Lin

Cheng-Ming Weng

Seng Wah Liau

Xu Yang Shen

Yen-Liang Lu

Bao-Tzeng Huang

Yi-Ting Liao

Yun Tzu Chang

Fang-Yi Liu

A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Field effect transistor and fabrication method thereof

A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

Method for forming a thin film resistor with improved thermal stability

A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

MRAM structure and method of fabricating the same

An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

ReRAM structure and method of fabricating the same

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

Method for fabricating semiconductor device

An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.

Integrated circuit device and method of fabricating integrated circuit

Semiconductor device and method for fabricating the same

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

Semiconductor structure and manufacturing method thereof

A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.

Semiconductor device and method for forming the same

A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

Semiconductor process for forming plug

A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

Semiconductor process

A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.

Method for fabricating a MIM capacitor

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Tainan, Taiwan

Kuo-Chih Lai