Nan Ya Technology Corporation

Kuo-Chien Wu

Shih-Fan Kuan

Ping Cheng Hsu

Yi-Nan Chen

Tse-Yao Huang

Jeng-Ping Lin

Chang-Rong Wu

Yinan Chen

Sweehan J H Yang

Hung-Chang Liao

A word line structure with a single-sided partially recessed gate structure. The word line structure includes a gate structure, a first gate spacer, and a second gate spacer. The gate structure includes a gate dielectric layer, a first gate layer, a second gate layer, and a gate capping layer and has a recess region adjacent to one of opposing sidewalls of the second gate layer. The first gate spacer is disposed over opposing sidewalls of the gate dielectric layer and the first gate layer. The second gate spacer is disposed over opposing sidewalls of the gate structure and covers the first gate spacer. A method for forming a word line structure with a single-sided partially recessed gate structure is also disclosed.

Word line structure with single-sided partially recessed gate structure

A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of: forming a thin nitride insulating layer on a gate structure and a diffusion region of the transistor; forming a first insulating layer, which is then planarized to expose the nitride insulating layer on the gate structure; etching through the first insulating layer to form a first part of a contact hole; forming a first part of a contact in said first part of the contact hole; forming a second insulating layer; etching through the second insulating layer to form a second part of the contact hole; and forming a second part of the contact in the second part of the contact hole. The two-stage etching process for forming a conductive contact effectively prevents over-etching and short-circuiting between a wordline and a bitline.

Method for forming self-aligned contact in semiconductor device

A bitline structure for DRAM and the method for forming the same. The bitline structure includes a first dielectric layer on a substrate, a bitline contact hole, formed through the first dielectric layer, a bitline contact, formed in the bitline contact hole, a second dielectric layer, formed on the first dielectric layer and covering the bitline contact, a peripheral contact hole, formed through the first dielectric layer and the second dielectric layer, a peripheral contact, formed in the peripheral contact hole, a first bitline, formed in the second dielectric layer and contacting the bitline contact, and a second bitline, formed in the second dielectric layer and contacting the peripheral contact.

Bitline structure for DRAM and method of forming the same

A method for forming a bit line. A semiconductor substrate is provided. A MOS having a gate and an S/D area is formed on the semiconductor substrate. A first dielectric layer with a first opening is formed on the semiconductor substrate to expose the S/D area. A conducting layer is formed in the first opening. A barrier layer is formed on the surface of the first dielectric layer and the conducting layer. A second dielectric layer having a second opening and a third opening is formed on the barrier layer, the position of the second opening corresponding to the first opening. Metal layers are formed in the second opening and the third opening as bit lines, respectively.

Method for forming bit line

Disclosed is a method for manufacturing deep trench structure comprising the steps of providing a substrate; forming a deep trench in the substrate; forming a nitride layer in the deep trench; filling the deep trench with a first conductive layer; removing a portion of the nitride layer not covered by the first conductive layer; refilling the deep trench with another nitride layer so that the sidewall of the deep trench not covered by the first polymer, is covered; partially removing the refilled nitride layer; forming a collar oxide layer in the deep trench; filling the deep trench with a second conductive layer; removing a portion of the collar oxide layer not covered by the second conductive layer; and filling the deep trench with a third conductive layer.

Deep trench structure manufacturing process

A method for avoiding short circuits between conductive wires. The method includes providing a substrate having a contact area, forming a first opening in the substrate to expose the contact area, filling the first opening with a first conductive material to form a first conductive layer, removing a portion of the first conductive layer to form a second opening, in order to expose a sidewall of the substrate, forming a spacer on the sidewall, depositing a poly-silicon layer over the substrate to fill the second opening to form a second conductive layer, etching back the poly-silicon layer to expose a portion of the spacer, forming a patterned dielectric layer over the substrate to define a wire opening in order to expose the second conductive layer, and filling the wire opening with a third conductive material to form a wire electrically connected with the second conductive layer.

Method for avoiding short-circuit of conductive wires

World line structure with single-sided partially recessed gate structure

A method for fabricating a deep trench capacitor. A substrate is provided having a pad oxide layer and a pad nitride layer stacked on a main surface thereof. A deep trench is etched into the substrate through the pad oxide layer and the pad nitride layer. A node dielectric is coated on the interior surface of the deep trench. A silicon spacer layer is formed on the sidewall of the deep trench over the node dielectric. An upper portion of the silicon spacer layer is doped with dopants such as BF. The undoped portion of the silicon spacer layer is selectively removed to expose a portion of the node dielectric. The exposed node dielectric is stripped off to expose the substrate. The remaining node dielectric covered by the doped silicon spacer layer forms a protection spacer for protecting the pad oxide layer from corrosion during the subsequent etching processes.

Method for fabricating a trench capacitor of DRAM

A method of fabricating a semiconductor device. A stack gate structure having a cap layer thereon and a first dielectric layer having a top surface that exposes the cap layer are formed on a substrate. A buffer layer is formed to cover the dielectric layer and the cap layers in a first region of the substrate. A portion of the cap layers in a second region of the substrate are removed so that the cap layers have a thickness smaller than or equal to the buffer layer. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer and the underlying the buffer layer and the first dielectric layer are etched to form a bit line contact opening. In the meantime, a portion of the second dielectric layer and the underlying cap layer are etched to form a gate contact opening.

Method of fabricating semiconductor device

A method for making a deep trench capacitor is disclosed. A substrate with a deep trench formed therein is provided. The trench is doped to form a buried plate electrode serving as a first electrode of the deep trench capacitor at a lower portion of the trench. A node dielectric is formed on interior surface of the trench. Subsequently, the trench is filled with a first conductive layer and then recessed to a first depth. A collar oxide layer is then formed on vertical sidewall of the trench on the first conductive layer. The trench is filled with a second conductive layer and again recessed to a second depth. A pair of symmetric spacers is then formed on the vertical sidewall of the trench. A third conductive layer is deposited on the second conductive layer and on the symmetric spacers, and fills the trench. The trench is recessed to a third depth.

Method for fabricating a trench capacitor

A method of reducing trench aspect ratio. A trench is formed in a substrate. A conformal Si-rich oxide layer is formed on the surface of the trench by HDPCVD. A conformal first oxide layer is formed on the Si-rich oxide layer by HDPCVD. A conformal second oxide layer is formed on the first oxide layer by LPCVD. Part of the Si-rich oxide layer, the second oxide layer and the first oxide layer are removed by anisotropic etching to form an oxide spacer composed of a remaining Si-rich oxide layer, a remaining second oxide layer and a remaining first oxide layer. The remaining second oxide layer, part of the remaining first oxide layer and part of the Si-rich oxide layer are removed by BOE. Thus, parts of the remaining first and Si-rich oxide layers are formed on the lower surface of the trench, thereby reducing the trench aspect ratio.

Method of reducing the aspect ratio of a trench

A method of fabricating a memory device having a deep trench capacitor is described. A first conductive layer is formed in the lower and middle portions of a deep trench in a substrate. An undoped semiconductor layer is formed in the upper portion of the deep trench. A mask layer is formed on the substrate, wherein the mask layercovers the periphery of the undoped semiconductor layer that is adjacent to the neighboring region, pre-defined for the active region of the deep trench. An ion implantation process is performed to implant dopants into the undoped semiconductor layer exposed by the mask layer so as to form a second conductive layer. The first and the second conductive layers constitute the upper electrode of the deep trench capacitor.

Method for fabricating memory device having a deep trench capacitor

A method for manufacturing a gate structure has the steps of providing a substrate; forming a conducting layer on the substrate; forming a metal layer on the conducting layer; forming a patterned first protective layer on the metal layer, the protective layer having a side surface; partially removing the side surface of the first protective layer to form a first gate element having a first gate pattern; transferring the first gate pattern to the metal layer to form a second gate element; conformally forming a second protective layer on the first gate element, the second gate element and the conducting layer, causing a second gate pattern; and transferring the second gate pattern to the conducting layer to form a third gate element.

Method for manufacturing gate structure with sides of its metal layer partially removed

A semiconductor device and method of manufacturing the same are disclosed. A conductive structure, spacers and a dielectric layer are formed on a substrate. Thereafter, a portion of the cap layer, a portion of the spacers and a portion of the dielectric layer of the conductive structure are removed to form a funnel-shaped opening. The shoulder section of the conductive layer exposed by the funnel-shaped opening is removed to form a shoulder recess. A liner layer is formed on the sidewall of the funnel-shaped opening and then a bottom plug is formed inside the funnel-shaped opening. Another dielectric layer is formed over the substrate. A top plug is formed in the dielectric layer such that the top plug and the bottom plug are electrically connected. Finally, a wire line is formed over the substrate.

Method of manufacturing semiconductor device featuring formation of conductive plugs

Disclosed is a method for forming bit line and bit line contact structure. Based on a semi-finished structure with a poly plug filled in a contact window, the method of the Invention comprises steps of removing some of the oxide layer so that the plug protrudes, oxidizing the exposed region of the protruding portion of the plug, removing the oxidized portion of the plug, forming a first dielectric layer to the upper surface of the resultant structure, wherein the upper surface of the plug is exposed, forming a second dielectric layer to the upper surface of the first dielectric layer including the upper surface of the plug, forming photoresist on the second dielectric layer, then performing exposing, developing and etching to form a trench of a predetermined pattern, and filling metal into the trench to form a bit line.

Growing community of inventors

Miaoli, Taiwan

Kuo-Chien Wu