Nan Ya Technology Corporation

Kuo-Chiang Wang

A memory device is disclosed. The memory device includes a memory array, a protection circuit, and a control circuit. The memory array includes several memory rows. The protection circuit is configured to determine a first row of the several memory rows to be a victim row. The control circuit is coupled to the memory array and the protection circuit, and the control circuit is configured to back up a data stored in the first row to a second row of the several memory rows. The victim row is hammer attacked.

Memory device and protection method thereof

A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a memory cell array, a memory interface, a first peripheral circuit, and a second peripheral circuit. The first peripheral circuit supports a first memory protocol, and the second peripheral circuit, supports a second memory protocol different from the first memory protocol. The first peripheral circuit and the second peripheral circuit share the memory cell array and the memory interface.

Growing community of inventors

Taoyuan, Taiwan

Kuo-Chiang Wang