Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo-Chiang Tsai

Jyh-Huei Chen

Fu-Hsiang Su

Ke-Jing Yu

Yi-Ju Chen

Jye-Yen Cheng

Chih-Hong Hwang

Jhy-Huei Chen

Szu-Wei Tseng

Hsin-Huang Lin

Jeng-Ya David Yeh

Mu-Chi Chiang

Tien-Hung Cheng

A semiconductor device includes a source via having a body portion and a barrier layer surrounding the body portion, and the body portion is in physical contact with the source contact. Furthermore, the barrier layer includes at least one sidewall section separating the source via from an adjacent via structure. As such, the via to via leakage may be prevented. Overall, by providing a semiconductor device having the above structures, the contact resistance is reduced, and the device performance is further improved.

Semiconductor device and method of fabricating the same

One or more active region structures each protrude vertically out of a substrate in a vertical direction and each extend horizontally in a first horizontal direction. A source/drain component is disposed over the one or more active region structures in the vertical direction. A source/drain contact is disposed over the source/drain component in the vertical direction. The source/drain contact includes a bottom portion and a top portion. A protective liner is disposed on side surfaces of the top portion of the source/drain contact but not on side surfaces of the bottom portion of the source/drain contact.

Protective liner for source/drain contact to prevent electrical bridging while minimizing resistance

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed over the gate stack, wherein the first metal layer laterally contacts the spacers over the gate dielectric layer and the gate electrode; and a gate via disposed over the first metal layer.

Semiconductor device with reduced contact resistance and methods of forming the same

Semiconductor structures and method for manufacturing the same are provided. The method includes forming a first conductive structure over a substrate and forming a second conductive structure through a dielectric layer over the first conductive structure. The method further includes partially removing the dielectric layer to reduce a thickness of the dielectric layer along a first direction and forming a third conductive structure over the second conductive structure. In addition, a first portion of the third conductive structure is within a projection area of the second conductive structure along the first direction, and a second portion of the third conductive structure is outside the projection area of the second conductive structure along the first direction, and a first bottom surface of the first portion is spaced apart from a second bottom surface of the second portion by a distance along the first direction.

Method for manufacturing semiconductor structure having raised via contacts

A method includes receiving a semiconductor structure having a source contact feature electrically connected to a source feature and a drain contact feature electrically connected to a drain feature. The method includes etching to form a drain via trench over the drain contact feature and forming a drain via in the drain via trench. After forming the drain via, the method further includes etching to form a source via trench over the source contact feature and forming a source via in the source via trench. The drain via has a first dimension along a first direction, the source via has a second dimension along the first direction, and the second dimension is greater than the first dimension.

Methods of manufacturing via structures on source/drain contacts

FinFET devices with source/drain contacts with reduced resistance/capacitance power loss and with an enhanced processing window between the source/drain contacts and a gate via and methods of manufacture are described herein. A metal riser may be formed in a first recess of a source/drain contact of a first material. The metal riser and a contact via may be formed from a second material and the contact via may be formed over the metal riser to provide a hybrid source/drain contact of a finFET with a wide surface contact area at an interface between the source/drain contact and the metal riser. A dielectric fill material and/or a conformal contact etch stop layer may be used to form an isolation region in a second recess of the source/drain contact to extend a processing window disposed between the isolation region and a gate contact of the finFET.

Semiconductor devices and methods of manufacture

A semiconductor device includes a gate disposed over a substrate. A source/drain is disposed in the substrate. A conductive contact is disposed over the source/drain. An air spacer is disposed between the gate and the conductive contact. A first component is disposed over the gate. A second component is disposed over the air spacer. The second component is different from the first component.

Gate air spacer protection during source/drain via hole etching

A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A gate dielectric layer covers opposite sidewalls and a bottom of the conductive gate stack. A first gate spacer layer and a second gate spacer layer respectively cover portions of the gate dielectric layer corresponding to the opposite sidewalls of the conductive gate stack. A source/drain contact structure is separated from the conductive gate stack by the gate dielectric layer and the first gate spacer layer. A first insulating capping feature covers the conductive gate stack and is separated from the second gate spacer layer by the gate dielectric layer, and a second insulating capping feature covers the source/drain contact structure. An upper surface of the second insulating capping feature is substantially level with an upper surface of the first insulating capping feature.

Contact structure with insulating cap

An exemplary semiconductor device includes a substrate, a first conductive feature, a second conductive feature, and a third conductive feature over the substrate. The first conductive feature has a first top surface and a side surface. The third conductive feature is on the first top surface of the first conductive feature and is spaced away from the second conductive feature. The third conductive feature has a first sidewall and a second sidewall opposing the first sidewall. The first sidewall extends between the first conductive feature and the second conductive feature. At least a segment of the first sidewall has a first slope. The second sidewall has a second slope. The second slope is greater than the first slope.

Contact and via structures

A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a conductive capping feature formed on and in direct contact with the gate electrode layer. The semiconductor device structure includes a source/drain (S/D) contact structure formed over the substrate and adjacent to the gate electrode layer, and an air gap is adjacent to the S/D contact structure, and the air gap is lower than the conductive capping feature.

Insulating cap on contact structure

In one example, a semiconductor device includes a first conductive feature embedded in a first dielectric layer such that a top surface of the first dielectric layer is higher than a top surface of first conductive feature, a contact etch stop layer (CESL) disposed on the first dielectric layer, and a second conductive feature embedded in a second dielectric layer. The second dielectric layer is disposed on the CESL and the second conductive feature extends through the CESL and is in direct contact with the first conductive feature.

Conductive element for semiconductor devices

A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A first gate spacer is formed adjacent to a sidewall of the conductive gate stack. A source/drain contact structure is formed adjacent to the first gate spacer. An insulating capping layer covers and is in direct contact with an upper surface of the conductive gate stack. A top width of the insulating capping layer is substantially equal to a top width of the conductive gate stack. The insulating capping layer is separated from the source/drain contact structure by the first gate spacer.

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Hsinchu, Taiwan

Kuo-Chiang Tsai