Holtek Microelectronics Inc.

Other

Industrial Technology Research Institute

Utek Semiconductor Corporation

Kuo Cheng Yu

I Liang Fang

Jason Chen

Wu Chi Yung

Hwei M Lee

The present invention provides a method for accessing a memory device and a memory accessing device. The method includes a) providing the memory device having a plurality of memory sub-spaces respectively having a plurality of address ranges; b) respectively assigning a plurality of base addresses to the plurality of memory sub-spaces; c) inputting an access address; d) respectively operating the base addresses with the access address to obtain a plurality of operated results; and e) accessing one of the memory sub-spaces if a specific one of the operated results falls within one of the address ranges corresponding to the one memory sub-space. The memory accessing device includes an access address end, a data access end, an access selection end, a memory device having a plurality of memory sub-spaces, and a plurality of access devices respectively electrically connected to the memory sub-spaces, and each of which includes a base address storing device for storing therein a base address, an operating and comparing device for operating the access address with the base address to obtain an operated result and generating a data access enabling signal when the operated result falls within an address range, and a data buffer for accessing the respective memory sub-space in response to the data access enabling signal and the access selection signal.

Method of and means for accessing an address by respectively

The mechanism includes a virtual address detecting circuit for detecting the virtual address of the instruction code. When a virtual address is detected, an indicating signal is generated, which is then sent to an indirect address register to register the indirect address of the instruction code. Thereafter, an indirect address replacing circuit is used to decode and replace the indirect address registered in and sent from the indirect address register with a direct address. In the absence of the virtual address, the direct address is allowed to pass through the indirect address replacing circuit.

Instruction decoding mechanism for reducing execution time by earlier

An improved micro-controller with a built-in test circuit is disclosed. It contains: (a) a test-mode switching register for receiving an external instruction from a test instrument so to select a test mode and to switch the external instruction to a predetermined circuit according to a selected test mode; (b) a test control circuit electrically connected to the test-mode switching register for controlling a timing of the external instruction received from the test instrument; (c) a multiplexer electrically connected to the test control circuit to receive an output signal from the test control circuit; (d) a control circuit electrically connected to the multiplexer for receiving an output signal therefrom, wherein the control circuit decodes and executes the output signal from the multiplexer, and sends an executing result to the test instrument; (e) a test program memory electrically connected to the multiplexer for storing a built-in test program, so as to allow the micro-controller to be tested in an internal mode; (f) an application program memory for storing an application program; and (g) a ROM read-out device electrically connected to the multiplexer and the application program memory for reading program codes from the application program memory to facilitate the test instrument to make a comparison.

Micro-controller with a built-in test circuit and method for testing the

The present invention is related to a system reset device setting the reset status of a system in response to a reset signal. The system reset device according to the present invention includes a power-stability detecting circuit for detecting the stability of a power signal generated by a power source and provided for the system, an oscillation-stability detecting circuit for detecting the stability of an oscillation signal generated by an oscillator and provided for the system, and a level-control circuit electrically connected to the power-stability detecting circuit and the oscillation-stability detecting circuit for controlling a level state of the rest signal in response to the stability of the power signal and the oscillation signal. The level-control circuit includes an OR gate, an AND gate, and an S-R latch for performing the level state control of the reset signal.

System reset device having level controller for opportunely setting

A memory table look-up method for executing a table look-up instruction in an active program uses an instruction buffer executing device, a controller and a data register to output table look-up data from a memory to the data register. The method includes causing an instruction buffer executing device to execute a table look-up instruction obtained from the memory and pre-stored in the instruction buffer executing device in a first cycle to generate and output a table look-up signal, and to cause the controller to output a next instruction being an instruction next to the table look-up instruction in the active program from the memory to the instruction buffer executing device in response to the table look-up signal. The method further includes the step of causing the controller to generate a forbidding signal in a second cycle for latching the next instruction located in the instruction buffer executing device, and to generate and output a write-in instruction to the instruction buffer executing device for generating a write-in signal in order to output said table look-up data to the data register.

Memory table look-up device and method

A flag setting circuit for a microcontroller, which can be set with a HALT mode flag and a watchdog timer overflow flag by using a system power-on signal, an external reset signal, a watchdog timer overflow signal inside the microcontroller, a clear instruction for watchdog timer, a HALT mode instruction, and a wake-up signal. The setting circuit for the watchdog timer overflow flag includes a reset signal generator, a watchdog timer, a clear signal generator, a flag clear circuit, and a register circuit. The setting circuit for the HALT mode flag includes a HALT mode discerning circuit, a flag clear circuit, and a register circuit. The frequency source of the watchdog timer is provided by means of a frequency from the system oscillator divided with four, or by using a frequency of RC oscillator built in the system. Under the HALT mode, the RC oscillator is selected. By means of the HALT mode flag and the watchdog timer overflow flag, the operation condition of the system hardware can be discerned.

Growing community of inventors

Hsinchu, Taiwan

Kuo Cheng Yu