Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Kuo-Cheng Lee

Yun-Wei Cheng

Chun-Hao Chou

Hsin-Chi Chen

Yung-Lung Hsu

Hsun-Ying Huang

Feng-Chien Hsieh

Tsung-Han Tsai

Yen-Liang Lin

Volume Chien

Chia-Yu Wei

Chi-Cherng Jeng

Yin-Chieh Huang

Chun-Wei Chia

Cheng-Ming Wu

Ying-Hao Chen

Chiu-Jung Chen

Zhe-Ju Liu

Wei-Li Hu

Cheng-Yuan Li

Ping-Hao Lin

Kun-Huei Lin

Wei-Lin Chen

Horng-Huei Tseng

Fu-Cheng Chang

Chao-Hsiung Wang

Tzu-Hsuan Hsu

Shiu-Ko JangJian

Ching-Chung Su

Yi-Hsing Chu

Chun-Liang Lu

Shyh-Fann Ting

Hsin-Chieh Huang

Shih-Hsun Hsu

Ming-Hsien Yang

Kai-Chun Hsu

Wan-Chen Huang

Po-Han Chen

Yu Ting Kao

Chung-Liang Cheng

Ching-Chun Wang

Ching-Hung Kao

Wen-I Hsu

Chia-Pin Cheng

Yen-Hsung Ho

Horng Huei Tseng

Li-Wen Huang

Chia Chun-Wei

Bo-Tsung Tsai

Chuan-Pu Liu

Chih-Cherng Jeng

Mu-Han Cheng

Chen-Chun Chen

Allen Tseng

Huan-En Lin

Chun-Lin Fang

Ting-Hao Chang

Chia-Yen Hsu

Yu-Ting Kao

Ping Kuan Chang

Chun-Hao Lin

ChunHao Lin

Cheng Yuan Wang

Dun-Nian Yaung

Jen-Cheng Liu

Feng-Chi Hung

Sheng-Chau Chen

Ching-Hwanq Su

Chia-Jung Hsu

Wei-Ming You

Po-Zen Chen

Chien Nan Tu

Szu-Hung Yang

Chun-wen Cheng

Yu-Cheng Tsai

Ssu-Chiang Weng

Chen Hsin-Chi

Feng-chi Hung

Chi-Chin Hsu

Yu-Shen Shih

Chen Chiu-Jung

Kuan-Ling Pan

Cheng-Hao Chiu

Jung-huei Peng

Yin Chieh Huang

Kuan-Fu Lu

Yu Ling Ou

Bo-Ge Huang

A stacked CMOS image sensor (CIS) structure is provided. The stacked CIS structure comprises a first die, a second die and a third die. The first die comprises a photodiode, a transfer gate, a selective conversion gain (SCG) switch, a reset switch, a floating node diffusion capacitor and a SCG diffusion capacitor. The second die comprises a source follower transistor and a row select switch. The third die comprises an image sensing circuit electrically connected to the third floating node.

Multi-wafer stacked CMOS image sensor structure

A pixel sensor may include a main deep trench isolation (DTI) structure and one or more sub-DTI structures in a substrate of the pixel sensor to increase the quantum efficiency of the pixel sensor at large incident angles. The one or more sub-DTI structures may be located within the perimeter of the main DTI structure and above a photodiode. The one or more sub-DTI structures may be configured to provide a path of travel for incident light into the photodiode from large incident angles in that the one or more sub-DTI structures may be filled with an oxide material to increase light penetration into the one or more sub-DTI structures. This may reduce reflections at a top surface of the substrate, thereby permitting incident light to refract into the substrate and toward the photodiode.

Pixel sensor including refraction structures

The present disclosure provides a high-dynamic range (HDR) pixel circuit, which includes a pixel subcircuit and a light-responsive switch circuit. The pixel subcircuit includes a photodetector, a capacitor, and a source-follower transistor. The source-follower transistor is enabled using a power supply voltage provided by the light-responsive switch circuitin response to the HDR pixel circuit being in a low light illuminance. The source-follower transistor is enabled using a first voltage generated by the photodetector in response to the HDR pixel circuit being in a high light illuminance. A first voltage detected by the photodetector and a second voltage associated with electric charges stored in the capacitor are outputted to form a HDR pixel value.

High dynamic-range (HDR) pixel circuit, color-image sensor package structure, and method for operating HDR pixel circuit

An image sensor device may include a pixel sensor array and a black level correction (BLC) region. The BLC region may include a sensing region in a substrate and a light-blocking layer above the sensing region. An anti-reflection array may be formed in the light-blocking layer. The anti-reflection array includes holes, trenches, and/or other structural features such that the light-blocking layer includes two or more areas in which the top surface of the light-blocking layer is at different heights in the image sensor device. The different heights of the top surface of the light-blocking layer reduce the likelihood of light being reflected off of the light-blocking layer and toward the pixel sensor array. The anti-reflection array may reduce the likelihood of occurrence of flares or hot spots in images generated by the image sensor device, which may increase the image quality of the images generated by the image sensor device.

Image sensor device and methods of formation

A method of manufacturing a semiconductor wafer is disclosed. The method includes exposing the semiconductor wafer to one or more dopant species to form one or more first implant layers on the semiconductor wafer, testing one or more geometric parameter values of the formed one or more first implant layers, after testing the one or more geometric parameter values, conditionally exposing the semiconductor wafer to one or more dopant species to form one or more additional implant layers on the semiconductor wafer, after forming the one or more additional implant layers, conditionally forming one or more additional circuit layers on the semiconductor wafer to form a plurality of functional electronic circuits on the semiconductor wafer, and conditionally testing the semiconductor wafer with a wafer acceptance test (WAT) operation.

Mid-manufacturing semiconductor wafer layer testing

An optical device includes a substrate, a first electrode, a second electrode, and a first lens. The first electrode and the second electrode are over the substrate and configured to generate a first electric field. The first lens is between the first electrode and the second electrode and has a focal length that varies in response to the first electric field applied to the first lens.

Optical device and method of manufacturing the same

The present disclosure provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a sensing device, a solar cell, and an interconnecting structure. The solar cell is disposed above the sensing device and is electrically connected to the sensing device. The interconnecting structure is disposed between the sensing device and the solar cell and has a first surface facing the solar cell and a second surface facing the sensing devices. The interconnecting structure comprises a first energy storage component and a second energy storage component. The first energy storage component is disposed closer to the first surface of the interconnecting structure than the second energy storage component.

Semiconductor structure and method of manufacturing the same

An image sensor device includes a semiconductor substrate having a first side, and a trench isolation structure dividing the substrate into sensing units. Each sensing unit includes a first gate electrode and a second gate electrode disposed on the first side, and a first pixel and a second pixel extending into the substrate and disposed between the first and second gate electrodes from a top view perspective. The first pixel is disposed under the second pixel and electrically connected to the first gate electrode, and the second pixel is electrically connected to the second gate electrode. A method of manufacturing a semiconductor structure includes forming a trench isolation in a semiconductor substrate; forming a first pixel in the substrate; forming a second pixel in the substrate over the first pixel; forming a first gate structure over the substrate; and forming a second gate structure over the second pixel.

A semiconductor device may include a single-photon avalanche diode (SPAD) arranged for illumination at a back surface of a substrate. The semiconductor device may include a full deep trench isolation (FDTI) structure between the SPAD and a neighboring SPAD of the semiconductor device. The FDTI may be associated with isolating the SPAD from the neighboring SPAD. The FDTI structure may include a shallow trench isolation (STI) element at the back surface of the substrate. The FDTI structure may include a deep trench isolation (DTI) element at a front surface of the substrate.

Single-photon avalanche diode semiconductor device

A pixel sensor includes a transfer fin field effect transistor (finFET) to transfer a photocurrent from a photodiode to a drain region. The transfer finFET includes at least a portion of the photodiode, an extension region associated with the drain region, a plurality of channel fins, and a transfer gate at least partially surrounding the channel fins to control the operation of the transfer finFET. In the transfer finFET, the transfer gate is wrapped around (e.g., at least three sides) of each of the channel fins, which provides a greater surface area over which the transfer gate is enabled to control the transfer of electrons. The greater surface area results in greater control over operation of the finFET, which may reduce switching times of the pixel sensor (which enables faster pixel sensor performance) and may reduce leakage current of the pixel sensor relative to a planar transfer transistor.

Method for manufacturing image sensor including forming FinFET transfer gate having a plurality of channel fins above a p-type region

A grid structure in a pixel array may be at least partially angled or tapered toward a top surface of the grid structure such that the width of the grid structure approaches a near-zero width near the top surface of the grid structure. This permits the spacing between color filter regions in between the grid structure to approach a near-zero spacing near the top surfaces of the color filter regions. The tight spacing of color filter regions provided by the angled or tapered grid structure provides a greater surface area and volume for incident light collection in the color filter regions. Moreover, the width of the grid structure may increase at least partially toward a bottom surface of the grid structure such that the wider dimension of the grid structure near the bottom surface of the grid structure provides optical crosstalk protection for the pixel sensors in the pixel array.

Grid structure with at least partially angled sidewalls

A CMOS image sensor includes PDAF pixels distributed in an array of image pixels in plan view. Each PDAF pixel includes m×m binned photodiodes, a PDAF color filter overlying the binned photodiodes and laterally surrounded by a first isolation structure, and a PDAF micro-lens overlying the PDAF color filter. A first horizontal distance between a center of the PDAF color filter and a center of the binned photodiodes varies depending on a location of the PDAF pixel in plan view in the CMOS image sensor. Additionally, the first isolation structure includes a first low-n dielectric grid, a second low-n dielectric grid underlying the first low-n dielectric grid, and a metal grid enclosed by the second low-n dielectric grid. The second low-n dielectric grid includes a filler dielectric material different from a second low-n dielectric grid material. Thus, quantum efficiency and uniformity of the CMOS image sensor are improved.

CMOS image sensor

A pixel array includes a plurality of dark pixel sensors configured to generate dark current calibration information for a plurality of visible light pixel sensors included in the pixel array. The plurality of dark pixel sensors may generate respective dark current measurements for each of the plurality of visible light pixel sensors or for small subsets of the plurality of visible light pixel sensors. In this way, each of the plurality of visible light pixel sensors may be individually calibrated (or small subsets of the plurality of visible light pixel sensors may be individually calibrated) based on an estimated dark current experienced by each of the plurality of visible light pixel sensors. This may enable more accurate dark current calibration of the visible light pixel sensors included in the pixel array, and may be used to account for large differences in estimated dark currents for the visible light pixel sensors.

Pixel array including dark pixel sensors

A semiconductor arrangement includes a photodiode extending to a first depth from a first side in a substrate. An isolation structure laterally surrounds the photodiode and includes a first well that extends into a first side of the substrate. A deep trench isolation extends into a second side of the substrate and at least a portion of the deep trench isolation underlies the first well.

Semiconductor arrangement with isolation structure

The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.

Heat dissipation structures

Growing community of inventors

Tainan, Taiwan

Kuo-Cheng Lee