Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Parabellum Strategic Opportunities Fund LLC

Kuo-Cheng Ching

Chih-Hao Wang

Kuan-Lun Cheng

Ching-Wei Tsai

Carlos H Diaz

Zhiqiang Wu

Ying-Keung Leung

Shi Ning Ju

Chi-Wen Liu

Jean-Pierre Colinge

Shi-Ning Ju

Kuan-Ting Pan

Ka-Hing Fung

Guan-Lin Chen

Chao-Hsiung Wang

Zhi-Chang Lin

Chih-Sheng Chang

Ting-Hung Hsu

Wai-Yi Lien

Jiun-Jia Huang

Gwan Sin Chang

Ta-Pen Guo

Huan-Chieh Su

Li-Te S Lin

Chih-Liang Chen

Chun-Hsiung Lin

Wen-Hsing Hsieh

Chao-Hsien Huang

Jung-Hao Chang

Jhon Jhy Liaw

Chao-Cheng Chen

Bao-Ru Young

Ryan Chia-Jen Chen

Pei-Hsun Wang

Yuan-Sheng Huang

Jui-Chien Huang

Ching-Fang Huang

Hui-Wen Lin

Ting-Hua Hsieh

Teng-Chun Tsai

Kuo-Chi Tu

Keng-Chu Lin

Ming Zhu

Mao-Lin Huang

Wei-Hao Wu

Kuan-lun Cheng

Shu-Hao Kuo

Huicheng Chang

Jia-Ni Yu

Chung-Wei Hsu

Chung-Cheng Wu

Lung-Kun Chu

Harry Hak-Lay Chuang

Kuo-Yin Lin

Wen-Ting Lan

Chi-Yuan Chen

Wan-Chun Pan

Chun Chung Su

Ru-Gun Liu

Chi On Chui

Chih-Ming Lai

Chia-Hao Chang

Yen-Yu Chen

Cheng-Tung Lin

Cheng-Ting Chung

Kai-Chieh Yang

Hsiang-Pi Chang

Chun-Yao Chen

Gwan-Sin Chang

Hongfa Luan

Cary Chia-Chiung Lo

Chao Hsiung Wang

Sai-Hooi Yeong

Yu-Ming Lin

Harry-Hak-Lay Chuang

Yen-Ming Chen

Jiann-Tyng Tzeng

Lin-Yu Huang

Charles Chew-Yuen Young

Tien-Lu Lin

Jia-Chuan You

Li-Ting Wang

Wei-Liang Lin

Yi-Hsiung Lin

Sheng-Tsung Wang

Tzer-Min Shen

Chih-Chao Chou

Yu-Tien Shen

Chi-Hsing Hsu

Lei-Chun Chou

Chin-Yuan Tseng

Huey-Chi Chu

Ming-Liang Yen

Carlos Hernando Diaz

A semiconductor device structure includes a fin structure over a semiconductor substrate and a dummy gate stack formed over the fin structure and having a first sidewall and an opposite second sidewall. The semiconductor device structure also includes a first and second source or drain (S/D) structures in the fin structure and respectively adjacent to the first and second sidewalls of the dummy gate stack. The semiconductor device structure further includes an isolation feature formed in the fin structure below the dummy gate stack and having a third sidewall and an opposite fourth sidewall. A first end of the third sidewall overlaps the first end of the fourth sidewall. A second end of the third sidewall is in direct contact with a bottom of the dummy gate stack. A second end of the fourth sidewall is separated from the bottom of the dummy gate stack.

Structure of isolation feature of semiconductor device structure

FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

Fin-like field effect transistor patterning methods for achieving Fin width uniformity

Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Integrated circuits with finFET gate structures

Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.

Integrated circuits with gate cut features

A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.

Semiconductor device having fins and method of fabricating the same

Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first channel structure, a first gate dielectric layer surrounding the first channel structure, and a first metal gate surrounding first gate dielectric layer. The first metal gate includes a first metal layer in direct contact with the first gate dielectric layer and a first metal cap in direct contact with the first gate dielectric layer, wherein the first metal cap is in direct contact with the first metal layer.

Semiconductor device and method of forming thereof

A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.

Self-aligned spacers for multi-gate devices and method of fabrication thereof

A semiconductor structure includes a semiconductor fin, a doped dielectric fin, a shallow trench isolation (STI) oxide, a gate structure, and source/drain regions. The semiconductor fin upwardly extends from a substrate. The doped dielectric fin upwardly extends above the substrate. The doped dielectric fin is implanted with an impurity therein. The STI oxide laterally surrounds a lower portion of the semiconductor fin and a lower portion of the doped dielectric fin. The gate structure extends across the semiconductor fin and the doped dielectric fin. The source/drain regions are on the semiconductor fin and at opposite sides of the gate structure.

Semiconductor device and manufacturing method thereof

A semiconductor device includes first and second semiconductive fins, a first dielectric layer, a first gate structure, a spacer layer, and an oxide material. The first dielectric layer is laterally between the first and second semiconductive fins. From a cross-sectional view taken along a direction perpendicular to a lengthwise direction of the first semiconductive fin, the first dielectric layer has a U-shaped profile. The first gate structure extends across the first and second semiconductive fins and the first dielectric layer. The spacer layer underlies the first dielectric layer and further extends to laterally surround a lower portion of the first dielectric layer, a lower portion of the first semiconductive fin, and a lower portion of the second semiconductive fin. The oxide material is nested in the first dielectric layer. A top surface of the oxide material is at an elevation higher than a top surface of the spacer layer.

Semiconductor device with helmet structure between two semiconductor fins

Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.

FinFET devices and methods of forming the same

A semiconductor device is provided. The semiconductor device includes a plurality of channel layers stacked over a semiconductor substrate and spaced apart from one another, a source/drain structure adjoining the plurality of channel layers, a gate structure wrapping around the plurality of channel layers, and a first inner spacer between the gate structure and the source/drain structure and between the plurality of channel layers. The first inner spacer is made of an oxide of a semiconductor material.

Methods of fabricating semiconductor devices having gate-all-around structure with inner spacer last process

A semiconductor device includes a semiconductor fin, a gate structure, source/drain structures, and a contact structure. The semiconductor fin extends from a substrate. The gate structure extends across the semiconductor fin. The source/drain structures are on opposite sides of the gate structure. The contact structure is over a first one of the source/drain structures. The contact structure includes a semiconductor contact and a metal contact over the semiconductor contact. The semiconductor contact has a higher dopant concentration than the first one of the source/drain structures. The first one of the source/drain structures includes a first portion and a second portion at opposite sides of the fin and interfacing the semiconductor contact.

Semiconductor device having a Fin at a S/D region and a semiconductor contact or silicide interfacing therewith

Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.

Method for forming FinFET devices with a fin top hardmask

A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.

Multi-gate device and related methods

A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.

Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers

Growing community of inventors

Zhubei, Taiwan

Kuo-Cheng Ching