Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo-Cheng Chiang

Chih-Hao Wang

Kuan-Lun Cheng

Shi Ning Ju

Jia-Ni Yu

Lung-Kun Chu

Mao-Lin Huang

Kuan-Ting Pan

Chung-Wei Hsu

Zhi-Chang Lin

Shih-Cheng Chen

Jung-Hung Chang

Shi-Ning Ju

Ching-Wei Tsai

Guan-Lin Chen

Jia-Chuan You

Lo-Heng Chang

Yi-Ruei Jhan

Huan-Chieh Su

Jung-Chien Cheng

Wen-Ting Lan

Chi-Wen Liu

Pei-Hsun Wang

Kuan-lun Cheng

Chih-Chao Chou

Chien Ning Yao

Jui-Chien Huang

Ying-Keung Leung

Chia-Hao Chang

Li-Yang Chuang

Chun-Hsiung Lin

Chien-Ning Yao

Wei-Hao Wu

Chun-Fu Lu

Yen-Ming Chen

Carlos H Diaz

Wei-Sheng Yun

Tsung-Han Chuang

Cheng-Chi Chuang

Zhiqiang Wu

Tzu-Chiang Chen

Chao-Hsiung Wang

Shang-Wen Chang

Jin-Aun Ng

Yu-Ming Lin

Teng-Chun Tsai

Jean-Pierre Colinge

Hou-Yu Chen

Ka-Hing Fung

Ting-Hung Hsu

Hsiao-Han Liu

Lo Heng Chang

Ru-Gun Liu

Chih-Ming Lai

Jiann-Tyng Tzeng

Chih-Liang Chen

Hung-Li Chiang

Tung Ying Lee

Chao-Ching Cheng

Charles Chew-Yuen Young

I-Sheng Chen

Yu-Xuan Huang

Pei-Yu Wang

Cheng-Ting Chung

Yu-Lin Yang

Min Cao

Yi-Hsiung Lin

Yi-Bo Liao

Chen-Feng Hsu

Jiun-Jia Huang

Lei-Chun Chou

Kai-Lin Chuang

Chu-Yuan Hsu

Bo-Rong Lin

Kuo-Chi Tu

Chih-Sheng Chang

Chun-Yuan Chen

Sheng-Tsung Wang

Wei-Ting Wang

I-Han Huang

Hou-yu Chen

Wei Wang

Che-Chen Wu

Chia-Cheng Tsai

Yuan-Hsiang Wu

Chia-Hao Wang

Yi-Ruei Jihan

A method for forming a semiconductor device structure includes forming a fin structure, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack wrapped around the fin structure and forming a spacer layer extending along sidewalls of the fin structure and the gate stack. The method further includes partially removing the fin structure and the spacer layer to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers. A remaining portion of the spacer layer forms a gate spacer. In addition, the method includes forming an inner spacer layer along a sidewall and a bottom of the recess and partially removing the inner spacer layer using an isotropic etching process. Remaining portions of the inner spacer layers form multiple inner spacers. The method includes forming an epitaxial structure in the recess.

Structure and formation method of semiconductor device with epitaxial structures

A method for forming a semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first bottom layer formed adjacent to the first nanostructures, and a first insulating layer formed over the first bottom layer. The semiconductor device structure includes a first source/drain (S/D) structure formed over the first insulating layer, and the first insulating layer is in direct contact with one of the first nanostructures.

Semiconductor device structure and method for forming the same

A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers and a first source/drain epitaxial feature in contact with the plurality of semiconductor layers. The first source/drain epitaxial feature includes a bottom portion having substantially straight sidewalls. The structure further includes a spacer having a gate spacer portion and one or more source/drain spacer portions. Each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with one of the substantially straight sidewalls of the first source/drain epitaxial feature. The structure further includes a dielectric feature disposed adjacent one source/drain spacer portion of the one or more source/drain spacer portion. The dielectric has a second height substantially greater than the first height.

Semiconductor device structure and methods of forming the same

A method for forming a semiconductor structure is provided. The method includes forming first, second and third fin structures over a substrate, forming a first dielectric material along a first trench between the first fin structure and the second fin structure and along a second trench between the second fin structure and the third fin structure, removing a first portion of the first dielectric material along the second trench while leaving a second portion of the first dielectric material along the first trench as a dielectric liner, depositing a second dielectric material over the dielectric liner and filling the first trench and the second trench, and etching back the second dielectric material until the dielectric liner is exposed. A first portion of the second dielectric material remaining in the first trench forms a dielectric wall.

Semiconductor structure and method for forming the same

In some embodiments, the present disclosure relates to an integrated chip that includes a first nanosheet field effect transistor (NSFET). The first NSFET includes a first nanosheet channel structure arranged over a substrate, a second nanosheet channel structure arranged directly over the first nanosheet channel structure, and a first gate electrode structure. The first and second nanosheet channel structures extend in parallel between first and second source/drain regions. The first gate electrode structure includes a first conductive ring and a second conductive ring that completely surround outer sidewalls of the first nanosheet channel structure and the second nanosheet channel structure, respectively, and that comprise a first material. The first gate electrode structure also includes a passivation layer that completely surrounds the first and second conductive rings, is arranged directly between the first and second nanosheet channel structures, and comprises a second material different than the first material.

Tuning threshold voltage in nanosheet transitor devices

A method of independently forming source/drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source/drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source/drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source/drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source/drain region, the second inner spacer layer comprising a second material different from the first material.

Semiconductor device and method

A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a first nanostructure stack and a second nanostructure stack over the first fin and the second fin respectively. The method includes forming an isolation layer over the base. The method includes forming an isolation structure between the first fin and the second fin and between the first nanostructure stack and the second nanostructure stack. The isolation structure has an air gap. The method includes partially removing the isolation layer. The method includes forming a gate stack over the first nanostructure stack, the second nanostructure stack, the isolation structure, and the isolation layer.

Semiconductor device structure with air gap and method for forming the same

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

Method (and related apparatus) for forming a semiconductor device with reduced spacing between nanostructure field-effect transistors

A method of manufacturing a semiconductor device structure includes bonding a device substrate to a first de-bond layer. The first de-bond layer is disposed on a first carrier substrate, and the device substrate has a first side facing the first carrier substrate and a second side opposite from the first side. The device substrate has a first width. A front-end-of-line (FEOL) process and a back-end-of-line (BEOL) process are performed on the device substrate. A second carrier substrate having a second de-bond layer is bonded on the second side of the device substrate. The first carrier substrate is removed by removing the first de-bond layer. A width of the device substrate remains the first width after removing the first carrier substrate.

Trim free wafer bonding methods and devices

In a method of manufacturing a semiconductor device, a FET structure is formed over a substrate, which includes a plurality of semiconductor sheets vertically arranged over a bottom fin structure, a gate dielectric layer wrapping around each of the plurality of semiconductor sheets, a gate electrode disposed over the gate dielectric layer and a source/drain structure. A gate cap conductive layer is formed over the gate electrode, the bottom fin structure is replaced with a dielectric fin structure, spacers are formed on opposite sides of the dielectric fin structure, a trench is formed by etching the gate electrode using the dielectric fin and the spacers as an etching mask until the gate cap conductive layer is exposed, and the trench is filled with a first dielectric material.

Semiconductor device including spacers on sides of dielectric structure and manufacturing method thereof

In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers is formed, an isolation insulating layer is formed so that the stacked layer are exposed from the isolation insulating layer, a sacrificial cladding layer is formed over at least sidewalls of the exposed stacked layer, a sacrificial gate electrode is formed over the exposed stacked layer, an interlayer dielectric layer is formed, the sacrificial gate electrode is partially recessed to leave a pillar of the remaining sacrificial gate electrode, the sacrificial cladding layer and the first semiconductor layers are removed, a gate dielectric layer wrapping around the second semiconductor layer and a gate electrode over the gate dielectric layer are formed, the pillar is removed, and one or more dielectric layers are formed in a gate space from which the pillar is removed.

Method of manufacturing semiconductor devices and semiconductor devices

A structure includes a first dielectric feature extending along a first direction, the first dielectric feature having a first side and a second side opposing the first side. The structure includes a first semiconductor layer disposed adjacent the first side of the first dielectric feature, the first semiconductor layer extending along a second direction perpendicular to the first direction. The structure includes a CESL in contact with the first dielectric feature and a portion of the first semiconductor layer, an ILD layer in contact with the CESL and a portion of the first semiconductor layer. The structure further includes a second dielectric feature extending along the first direction, the second dielectric feature including a first dielectric layer in contact with the CESL and a portion of the first semiconductor layer, and a second dielectric layer in contact with the first dielectric layer and a portion of the first semiconductor layer.

Semiconductor device structure including forksheet transistors and methods of forming the same

The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Dielectric liner for field effect transistors

A method for forming a semiconductor transistor device includes forming a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The channel structure is formed by forming a stack of semiconductor layers. The gate structure is formed wrapping around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are formed on opposite endings of the channel structure. The gate contact is formed on the gate structure. The back-side source/drain contact is formed under the first source/drain epitaxial structure. The second source/drain epitaxial structure is formed to have a concave bottom surface.

Drain side recess for back-side power rail device

A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.

Transistors with stacked channels and the methods of forming the same

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Zhubei, Taiwan

Kuo-Cheng Chiang