Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo-Cheng Chiang

Chih-Hao Wang

Kuan-Lun Cheng

Shi Ning Ju

Jia-Ni Yu

Lung-Kun Chu

Mao-Lin Huang

Chung-Wei Hsu

Kuan-Ting Pan

Zhi-Chang Lin

Jung-Hung Chang

Shih-Cheng Chen

Shi-Ning Ju

Ching-Wei Tsai

Guan-Lin Chen

Jia-Chuan You

Yi-Ruei Jhan

Lo-Heng Chang

Huan-Chieh Su

Jung-Chien Cheng

Wen-Ting Lan

Chi-Wen Liu

Pei-Hsun Wang

Chih-Chao Chou

Jui-Chien Huang

Kuan-lun Cheng

Ying-Keung Leung

Chien Ning Yao

Chia-Hao Chang

Li-Yang Chuang

Chun-Hsiung Lin

Wei-Hao Wu

Chien-Ning Yao

Yen-Ming Chen

Carlos H Diaz

Chun-Fu Lu

Wei-Sheng Yun

Tsung-Han Chuang

Zhiqiang Wu

Chao-Hsiung Wang

Shang-Wen Chang

Yu-Ming Lin

Teng-Chun Tsai

Cheng-Chi Chuang

Tzu-Chiang Chen

Jean-Pierre Colinge

Ka-Hing Fung

Jin-Aun Ng

Ting-Hung Hsu

Lo Heng Chang

Ru-Gun Liu

Chih-Ming Lai

Jiann-Tyng Tzeng

Chih-Liang Chen

Tung Ying Lee

Chao-Ching Cheng

Charles Chew-Yuen Young

Hou-Yu Chen

Yu-Xuan Huang

Yu-Lin Yang

Min Cao

Yi-Hsiung Lin

Yi-Bo Liao

Chen-Feng Hsu

Jiun-Jia Huang

Lei-Chun Chou

Chu-Yuan Hsu

Kuo-Chi Tu

Hung-Li Chiang

Chih-Sheng Chang

I-Sheng Chen

Pei-Yu Wang

Cheng-Ting Chung

Wei-Ting Wang

Kai-Lin Chuang

Hou-yu Chen

Hsiao-Han Liu

Che-Chen Wu

Yuan-Hsiang Wu

Bo-Rong Lin

Chia-Hao Wang

Various embodiments of the present disclosure are directed towards an integrated chip including a first fin structure over a base region of a semiconductor substrate. A first plurality of semiconductor channel structures stacked vertically with one another over the base region of the semiconductor substrate. A first width of the first fin structure is different from a second width of the first plurality of semiconductor channel structures. A gate structure extends from the first fin structure to the first plurality of semiconductor channel structures.

Integration of multiple fin stuctures on a single substrate

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.

Isolation structures of semiconductor devices

A semiconductor device structure is provided. The structure includes a first gate electrode layer having at least three surfaces surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material. The structure also includes a second gate electrode layer disposed below and in contact with the first gate electrode layer, the second gate electrode layer having at least three surfaces surrounded by a second intermixed layer, wherein the second intermixed layer comprises the first material and a fifth material, wherein the first gate electrode layer and the second gate electrode layer are disposed between two adjacent dielectric spacers.

Semiconductor device having nanosheet transistor and methods of fabrication thereof

A method of forming a semiconductor device includes forming a fin of alternating layers of semiconductor nanostructures and sacrificial layers, laterally etching sidewall portions of the sacrificial layers, and depositing additional semiconductor material over the sidewalls of the semiconductor nanostructures and sacrificial layers. Following deposition of a dielectric material over the additional semiconductor material and additional etching, the remaining portions of the semiconductor structures and additional semiconductor material collectively form a hammer shape at each opposing side of the fin. Epitaxial source/drain regions formed on the opposing sides of the fin will contact the heads of the hammer shapes.

Enlargement of GAA nanostructure

A method for manufacturing a semiconductor structure is provided. The method includes forming a fin structure protruding from a substrate, wherein the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. The method includes forming a dummy gate structure across the fin structure. The method includes forming a gate spacer on the sidewall of the dummy gate structure. The method includes removing the dummy gate structure to expose the fin structure. The method includes partially removing the second semiconductor material layers to form concave portions on sidewalls of the second semiconductor material layers. The method includes forming dielectric spacers in the concave portions. The method includes removing the first semiconductor material layers to form gaps. The method includes forming a gate structure in the gaps to wrap around the second semiconductor material layers and the dielectric spacers.

Semiconductor and method for manufacturing the same

A device includes a substrate, a first semiconductor fin over the substrate extending in a first lateral direction, a first vertical stack of semiconductor nanosheets over the substrate extending in the first lateral direction, and an inactive fin between the first semiconductor fin and the first vertical stack extending in the first lateral direction. A first gate structure surrounds and covers the first semiconductor fin, and extends in a second lateral direction substantially perpendicular to the first lateral direction. A second gate structure surrounds and covers the first vertical stack, and extends in the second lateral direction.

Convergent fin and nanostructure transistor structure and method

A device includes a first vertical stack of nanostructures over a substrate, a second vertical stack of nanostructures over the substrate, a wall structure between and in direct contact with the first and second vertical stacks, a gate structure wrapping around three sides of the nanostructures and a source/drain region beside the first vertical stack of nanostructures.

Field effect transistor with asymmetrical source/drain region and method

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor fin over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, first and second dielectric layers over the substrate, and an S/D contact disposed on the epitaxial S/D feature. The first and second dielectric layers have different material compositions. A first sidewall of the epitaxial S/D feature is facing the first dielectric layer, a second sidewall of the epitaxial S/D feature is facing the second dielectric layer, and the S/D contact partially covers a top surface of the epitaxial S/D feature and extends continuously to cover the first sidewall of the epitaxial S/D feature.

Self-aligned source/drain metal contact

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure also includes a gate structure including a first portion wrapping around the first nanostructures and a second portion wrapping around the second nanostructures. The semiconductor structure also includes a dielectric feature sandwiched between the first portion and the second portion of the gate structure. In addition, the dielectric feature includes a bottom portion and a top portion over the bottom portion, and the top portion of the dielectric feature includes a shell layer and a core portion surrounded by the shell layer.

Method for manufacturing semiconductor structure with dielectric feature

A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.

Semiconductor device structure and methods of forming the same

Semiconductor devices using a dielectric structure and methods of manufacturing are described herein. The semiconductor devices are directed towards gate-all-around (GAA) devices that are formed over a substrate and are isolated from one another by the dielectric structure. The dielectric structure is formed over the fin between two GAA devices and cuts a gate electrode that is formed over the fin into two separate gate electrodes. The two GAA devices are also formed with bottom spacers underlying source/drain regions of the GAA devices. The bottom spacers isolate the source/drain regions from the substrate. The dielectric structure is formed with a shallow bottom that is located above the bottoms of the bottom spacers.

Semiconductor devices and methods of manufacture

Corner portions of a semiconductor fin are kept on the device while removing a semiconductor fin prior to forming a backside contact. The corner portions of the semiconductor fin protect source/drain regions from etchant during backside processing. The corner portions allow the source/drain features to be formed with a convex profile on the backside. The convex profile increases volume of the source/drain features, thus, improving device performance. The convex profile also increases processing window of backside contact recess formation.

Semiconductor devices with backside power rail and methods of fabrication thereof

A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.

Fin isolation structures of semiconductor devices

An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.

Integrated circuit with nanostructure transistors and bottom dielectric insulators

A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

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Zhubei, Taiwan

Kuo-Cheng Chiang