Micron Technology Incorporated

Kuo Chen Wang

Kunal R Parekh

David K Hwang

Wei Ming Liao

Wen Kuei Huang

Sriraj Manavalan

Ching Kai Lin

A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.

Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices

A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4Farchitecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.

Memory having buried digit lines and methods of making the same

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Boise, ID, United States of America

Kuo Chen Wang