Vanguard International Semiconductor Corporation

Industrial Technology Research Institute

Kuo-Chang Wu

Rong-Wu Chien

Ching-Ying Lee

Tzu-shih Yen

An improved alignment mark used by a laser trimming tool to locate fuses in an underlying integrated circuit is formed using conventional processing sequences. The design features high resolution and improved low noise characteristics. The alignment mark is etched in a shallow layer over a metal layer rather than in the metal itself. The edges which are sensed by the scanning alignment laser of the trimming tool have their elevated portions external to the alignment mark. The improved design replaces a prior art design in which the metal mark protruded from a deep area in the site region. Debris in deep areas adjacent to alignment marks etched in metal, is avoided by the improved design. The absence of this debris virtually eliminates noise in the alignment scan thereby greatly reducing alignment errors.

High contrast, low noise alignment mark for laser trimming of redundant memory arrays

A method for annealing a contact in a doped dielectric layer without the occurrence of dopant diffusion problem by depositing a sacrificial barrier layer of oxide material in the contact opening which is capable of preventing diffusion of dopant ions into the contact opening during a high temperature reflow process for the doped dielectric layer and followed by a deposition of an electrically conductive metal into the contact opening.

Method for contact anneal in a doped dielectric layer without dopant diffusion problem

A plasma etch method for forming a patterned silicon nitride layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket silicon nitride layer. There is then formed upon the blanket silicon nitride layer a patterned photoresist layer. Finally, there is etched through a plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket silicon nitride layer to form a patterned silicon nitride layer. The plasma etch method employs an etchant gas composition comprising a perfluorocarbon etchant gas, a hydrofluorocarbon etchant gas and an oxygen etchant gas at a perfluorocarbon etchant gas flow rate, a hydrofluorocarbon etchant gas flow rate and an oxygen etchant gas flow rate which yields substantially no plasma etch bias of the patterned silicon nitride layer with respect to the patterned photoresist layer. When the patterned silicon nitride layer is employed within a thermal oxidation mask, the blanket silicon nitride layer is only nearly completely patterned through the plasma etch method. The nearly completely patterned silicon nitride layer is then completely patterned and over-etched through a second plasma etch method, where the second plasma etch method employs a second etchant gas composition comprising a perfluorocarbon etchant gas, a hydrofluorocarbon etchant gas and an oxygen etchant gas at a perfluorocarbon etchant gas flow rate, a hydrofluorocarbon etchant gas flow rate and an oxygen etchant gas flow rate which minimizes etching of a blanket silicon oxide layer formed beneath the patterned silicon nitride layer within the thermal oxidation mask.

Pattern formation of silicon nitride

The present invention provides a method of forming a tapered polysilicon contact plug having reduced dimensions beyond the normal resolution limit of a photolithographic method by utilizing at least one polysilicon sidewall spacer as a mask in an anisotropic etching process of an oxide layer such that a contact window of reduced dimensions can be formed for the subsequent deposition of a heavily-doped polysilicon for forming the contact plug.

Method for forming tapered polysilicon plug and plug formed

A method for forming a gate with a tapered spacer is disclosed. The method includes forming a polysilicon layer on a substrate, and then forming a first oxide layer on the polysilicon layer. A photoresist layer is formed on the first oxide layer, where the photoresist layer defines a gate region, and then portions of the oxide layer and the polysilicon layer are removed using the photoresist layer as a mask, thereby forming a gate. A second oxide layer is formed on the substrate and the first oxide layer. Afterwards, the second oxide layer is isotropically etched so that the slope of the second oxide layer near the upper corners of the gate is reduced. Finally, the second oxide layer is anisotropically etched back to form spacers on the sidewalls of the gate.

Method for forming a tapered spacer

High contrast, low noise alignment mark for laser trimming of redundant

A method is described for etching contact openings through first and second interlevel dielectric layers covering the peripheral circuits of a DRAM integrated circuit to be electrically contacted in a semiconductor wafer is described. There is provided within and over the semiconductor wafer DRAM integrated circuit including peripheral circuits to be electrically contacted. A first conductive layer is formed over the DRAM integrated circuit and the layer is patterned. A first interlevel dielectric layer is formed over the first conductive layer which has been patterned. The first interlevel layer is composed of in the order from the first conductive layer of a silicon oxide layer and a borophosphosilicate layer. A second conductive layer is formed over the first interlevel dielectric layer and the second conductive layer is patterning said second conductive layer. A second interlevel dielectric layer is formed over the exposed second conductive layer and first interlevel dielectric. The second interlevel layer is composed of in the order from the second conductive layer of a borophosphosilicate layer and a silicon oxide layer. The openings through the first and second interlevel dielectric layers are etched to electrically contact regions in the peripheral circuits. The result due to the order of the interlevel dielectric layers the openings have an improved and positive slope characteristic.

Growing community of inventors

Taichung, Taiwan

Kuo-Chang Wu