Power Integrations, Inc.

Kuo-Chang Robert Yang

Sorin Stefan Georgescu

Hartley Fred Horwitz

Kamal Raj Varadarajan

Vijay Parthasarathy

Sujit Banerjee

Wayne Bryan Grabowski

Alexey Kudymov

Lin Zhu

Wayne Byran Grabowski

Georgescu Sorin Stefan

Capacitance networks for enhancing high voltage operation of high electron mobility transistors (HEMTs) are presented herein. A capacitance network, integrated and/or external, may be provided with a fixed number of capacitively coupled field plates to distribute the electric field in the drift region. The capacitively coupled field plates may advantageously be fabricated on the same metal layer to lower cost; and the capacitance network may be provided to control field plate potentials. The potentials on each field plate may be pre-determined through the capacitance network, resulting in a uniform, and/or a substantially uniform electric field distribution along the drift region.

Capacitance networks for enhancing high voltage operation of a high electron mobility transistor and method therein

Coupled polysilicon guard rings for enhancing breakdown voltage in a power semiconductor device are presented herein. Polysilicon guard rings are disposed above the power device drift region and electrically coupled to power device regions (e.g., device diffusions) so as to spread electric fields associated with an operating voltage. Additionally, PN junctions (i.e., p-type and n-type junctions) are formed within the polysilicon guard rings to operate in reverse bias with a low leakage current between the power device regions (e.g., device diffusions). Low leakage current may advantageously enhance the electric field spreading without deleteriously affecting existing (i.e., normal) power device performance; and enhanced electric field spreading may in turn reduce breakdown-voltage drift.

Coupled polysilicon guard rings for enhancing breakdown voltage in a power semiconductor device

Silicon carbide (SiC) junction field effect transistors (JFETs) are presented herein. A deep implant (e.g., a deep p-type implant) forms a JFET gate (). MET gate and MET source () may be implemented with heavily doped n-type (N+) and heavily doped p-type (P+) implants, respectively. Termination regions may be implemented by using equipotential rings formed by deep implants (e.g., deep p-type implants).

Silicon carbide junction field effect transistors

A switch having a drain, a source, and a control. The switch comprising a depletion-mode transistor including a first, a second, and a control terminal and an enhancement-mode transistor including a first, a second, and a control terminal. The first terminal of the depletion-mode transistor is the drain of the switch and the control of the depletion-mode transistor is coupled to the source of the switch. The control of the enhancement-mode transistor is coupled to the control of the switch, the second terminal of the enhancement-mode transistor is the source of the switch. The switch comprises a clamp circuit to clamp a voltage of the first terminal of the enhancement-mode transistor to a threshold, the clamp circuit comprises a resistor and a pn-junction device coupled between the first and second terminals of the enhancement-mode transistor and between the second terminal and the control of the depletion-mode transistor.

Clamp for a hybrid switch

A switch having a first terminal, a second terminal and a control terminal. The switch includes a normally-on device with a first terminal, a second terminal, and a control terminal. The first terminal of the normally-on device is the first terminal of the switch. The control terminal of the normally-on device is coupled to the second terminal of the switch. A normally-off device includes a first terminal, a second terminal, and a control terminal. The control terminal of the normally-off device is coupled to the control terminal of the switch. The second terminal of the normally off-device is the second terminal of the switch. The first terminal of the normally-off device is coupled to the second terminal of the normally-on device. A clamp circuit is coupled across the normally-off device. The clamp circuit is coupled to clamp a voltage of the first terminal of the normally-off device to a threshold.

A cascode switch circuit includes a normally-on device cascode coupled to a normally-off device between first and second terminals of the cascode switch circuit. A leakage clamp circuit is coupled between first and second terminals of the normally-off device. The leakage clamp circuit is coupled to clamp a voltage at an intermediate terminal between the normally-on device and the normally-off device at a threshold voltage level. The leakage clamp circuit is further coupled to clamp a voltage between the second terminal of the normally-on device and the control terminal of the normally-on device at the threshold voltage level to keep the normally-on device off when the normally-on device and the normally-off device are off.

A cascode switch circuit includes a normally-on device cascode coupled to a normally-of device between first and second terminals of the cascode switch circuit. A leakage clamp circuit is coupled between first and second terminals of the normally-off device. The leakage clamp circuit is coupled to clamp a voltage at an intermediate terminal between the normally-on device and the normally-off device at a threshold voltage level. The leakage clamp circuit is further coupled to clamp a voltage between the second terminal of the normally-on device and the control terminal of the normally-on device at the threshold voltage level to keep the normally-on device off when the normally-on device and the normally-off device are off.

A method includes defining, on a surface of a material, a plurality of discrete portions of a surface as surface elements having at least one of a laterally-varying size, a laterally-varying shape, and a laterally-varying spacing. A plurality of portions of the material beneath the surface elements are doped with a single quantity of dopant material per element area. The dopant material within the material beneath the surface elements expands to provide a lateral gradient of dopant material in the material beneath the surface elements.

Laterally-graded doping of materials

A vertical power transistor device includes a semiconductor layer of a first conductivity type, with a plurality of cylindrically-shaped dielectric regions disposed in the semiconductor layer. The cylindrically-shaped dielectric regions extend in a vertical direction from a top surface of the semiconductor layer downward. Adjacent ones of the cylindrically-shaped dielectric regions being laterally separated along a common diametrical axis by a narrow region of the semiconductor layer having a first width. Each dielectric region has a cylindrically-shaped, conductive field plate member centrally disposed therein. The cylindrically-shaped, conductive field plate member extends in the vertical direction from the top surface downward to near a bottom of the dielectric region. The dielectric region laterally separates the cylindrically-shaped, conductive field plate member from the narrow region. A source region is disposed at the top surface, and a drain region is disposed at the bottom, of the semiconductor layer.

Growing community of inventors

Campbell, CA, United States of America

Kuo-Chang Robert Yang