Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo-Bin Huang

Ming-Hsi Yeh

Ying-Liang Chuang

Chun-Hsiang Fan

Chun-Neng Lin

Ming-Chi Huang

Shun Wu Lin

Neng-Jye Yang

Jian-Jou Lian

Li-Min Chen

Po-Nan Yeh

Ju-Li Huang

Tsu-Hui Su

U-Ting Chiu

Yu-Wen Wang

Yu Shih Wang

Yu-Shih Wang

Yu-Chi Pan

Chun-Liang Tai

Chun-Chih Cheng

Ryan Chia-Jen Chen

Liang-Yin Chen

Chien-Hao Chen

Chia-Cheng Chen

Chia-Ying Lee

Chi-Chun Chen

Matt Yeh

Donald Y Chao

Yi-Hsing Chen

Shian Wei Mao

Chun-Cheng Chou

Hong-Jie Yang

Ssu-Yu Liao

Chia-Ling Chung

Ren-Kai Chen

Li-Chen Lee

Ta-Wei Lin

Kuan-Wei Lin

Wang-Hua Lin

Yu-Te Su

Kuo-Ju Chen

Jih-Churng Twu

Hsin-Hsien Lu

Jao Sheng Huang

Chia-Wei Wu

Ching-Shan Lu

Chieh-Yi Shen

Shih-Hsiang Chiu

Chun-Hung Chao

Yu-Fang Huang

Cheng-Chieh Tu

Chieh-Chun Chiang

Meng-Hsien Li

Shun-Wu Lin

Pei Yun Chung

Ying-Chuen Wang

Hao-Hsin Chen

Hao Yang

Hsiao-Chieh Chou

Li-min Chen

Tefu Yeh

Chih-Nan Lo

Disclosed is a method of forming gate structures for n-type and p-type transistors. The method includes: forming an interfacial layer and high-K (HK) dielectric layer for the gate structures; forming an n-type metal layer over the HK dielectric layer; forming a hard capping layer over the n-type metal layer while simultaneously strengthening the HK dielectric layer by fluorine passivation; patterning photo resist (PR) material over the hard capping layer that exposes a portion of the hard capping layer over the p-type transistor; removing the n-type metal layer and the hard capping layer over the p-type transistor via wet etching operations using high selectivity chemicals that are highly selective to the hard capping layer and the n-type metal layer; removing the patterned PR material while insulating, by the hard capping layer, gate structures from aluminum oxidation; and forming a p-type metal layer over the hard capping layer and the p-type transistor.

Metal gate patterning

Fin and nanostructured channel structure formation techniques for three-dimensional transistors can tune device performance. For example, fin profile control can be achieved by modifying the shape of fins/nanostructured channel structures so as to reduce their line edge roughness. Consequently, current flow within the channel regions of fins and nanostructured channel structures can be improved, enhancing device performance.

Fin shape modification

In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug.

Wet cleaning with tunable metal recess for via plugs

A method for manufacturing a semiconductor device includes forming a metal-including layer over a semiconductor substrate; forming a hydrophobic polymer layer over the metal-including layer; and forming an amphiphilic polymer layer between the metal-including layer and the hydrophobic polymer layer so as to enhance a bonding force therebetween.

Method for modifying metal-including material in semiconductor manufacturing process

An etchant for etching a cobalt-containing member in a semiconductor structure includes a fluorine-free acid and an alkaline solution, a rate of etching a cobalt-containing member by the etchant is greater than a rate of etching a nitride-containing member by the etchant, and a level of dissolved oxygen of the etchant is less than or equal to 100 ppb. A semiconductor structure, includes a plurality of epitaxial structures over a substrate, a gate structure over the substrate and between two of the plurality of epitaxial structures; a cobalt-containing member over one of the epitaxial structures and adjacent to the gate structure; and a dielectric member over the cobalt-containing member, wherein a top surface of the cobalt-containing member is formed by etching a portion of the cobalt-containing member using an etchant including a fluorine-free acid and an alkaline solution.

Etchant for etching a cobalt-containing member in a semiconductor structure and method of etching a cobalt-containing member in a semiconductor structure

A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

Method of breaking through etch stop layer

A method for manufacturing a semiconductor device includes forming one or more work function layers over a semiconductor structure. The method includes forming a hardmask layer over the one or more work function layers. The method includes forming an adhesion layer over the hardmask layer. The method includes removing a first portion of a patternable layer that is disposed over the hardmask layer. The adhesion layer comprises an organic acid that concurrently bonds metal atoms of the hardmask layer and phenol groups of the patternable layer, thereby preventing an etchant from penetrating into a second portion of the patternable layer that still remains over the hardmask layer.

Fin field-effect transistor and method of forming the same

A method of forming a semiconductor device includes the following steps. A metal layer with at least one silicon-containing pattern therein is provided. A first wet etching process is performed by using a first etching solution, to clean a surface of the metal layer, wherein the first etching solution contains a base and a first oxidant. At least one cycle is performed. Each cycle includes a second wet etching process and a cleaning process. The second wet etching process is performed by using a second etching solution, to remove the metal layer, wherein the second etching solution contains an acid and a second oxidant. A cleaning process is performed.

Semiconductor devices and method of forming the same

A method of fabricating a semiconductor device is described. A substrate is provided. A first semiconductor region of a first semiconductor material is formed over the substrate and adjacent a second semiconductor region of a second semiconductor material. The first and second semiconductor regions are crystalline. An etchant is selective to etch the first semiconductor region over the second semiconductor region. The entire first semiconductor region is implanted to form an amorphized semiconductor region. The amorphized semiconductor region is etched with the etchant using the second semiconductor region as a mask to remove the amorphized semiconductor region without removing the second semiconductor region.

Semiconductor devices and methods of manufacturing thereof

Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

Surface modification layer for conductive feature formation

A method of manufacturing a semiconductor device is provided. The method comprises the following steps of forming a first semiconductor layer over a substrate, the first semiconductor layer comprising a first semiconductor material; etching the first semiconductor layer to form a first recess; forming a second semiconductor layer in the first recess, the second semiconductor layer comprising a second semiconductor material different from the first semiconductor material; etching the first semiconductor layer and the second semiconductor layer to form a first fin comprising the second semiconductor layer and the first semiconductor layer; forming an insulation material over the substrate, wherein a top surface of the insulation material is flush with a top surface of the first fin; performing an implantation process on the first fin to form an implant region near the top surface of the first fin; and partially removing the insulation material to form shallow trench isolation regions, wherein the first fin is sandwiched by two adjacent shallow trench isolation regions.

Semiconductor device and manufacturing method thereof

The present disclosure is at least directed to utilizing air curtain devices to form air curtains to separate and isolate areas in which respective workpieces are stored from a transfer compartment within a workpiece processing apparatus. The transfer compartment of the workpiece processing apparatus includes a robot configured to transfer or transport ones of the workpieces to and from these respective storage areas through the transfer compartment and to and from a tool compartment. A tool is present in the tool compartment for processing and refining the respective workpieces. Clean dry air (CDA) may be circulated through the respective storage areas. The air curtains formed by the air curtain devices and the circulation of CDA through the respective storage areas reduces the likelihood of the generation of defects, damages, and degradation of the workpieces when present within the workpiece processing apparatus.

Air curtain device and workpiece processing tool

Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

Semiconductor device and method

A method includes depositing a first work function layer over a first and second gate trench. The method includes depositing a second work function layer over the first work function layer. The method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. The method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.

A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

Controlling fin-thinning through feedback

Growing community of inventors

Jhubei, Taiwan

Kuo-Bin Huang