Kabushiki Kaisha Toshiba

Kuniyoshi Yoshikawa

Seiichi Mori

Junichi Miyamoto

Masaki Sato

Kiyomi Naruke

Nobuaki Ohtsuka

Seiji Yamada

Yohei Hiura

The present invention discloses the new structure with regard to a nonvolatile semiconductor memory which can store therein an information corresponding to a plurality of bits. The nonvolatile semiconductor memory according to the present invention has a charge trapping layer for accumulating electrons, in an end of a gate electrode. In the nonvolatile semiconductor memory according to the present invention, the electrons are stored in this charge trapping layer to thereby store the information corresponding to the plurality of bits.

Method for manufacturing semiconductor memory

Semiconductor Memory

When the upper limit value of a leakage current allowed by a read.detection/write circuit connected to a plurality of bit lines to read and write data from and in memory cells is represented by IL, Vs satisfies ##EQU1## (ln is the natural logarithm) where Vgh is the potential of a non-selected word line, Vta is the average threshold voltage of the memory cells, e is the standard deviation, s is the subthreshold coefficient, Vd is the potential of the bit lines, and Vs is the potential of a source line.

Semiconductor memory device with a plurality of memory cells connected

An SiO.sub.2 film and a PSG film are stacked on a semiconductor substrate. A contact hole is formed through the both films. An Si.sub.3 N.sub.4 film is formed on a side wall of the contact hole as a free ion Na.sup.+ blocking film. An aluminum wiring layer is formed in the contact hole. This arrangement prevents free ions Na.sup.+ from externally migrating through the SiO.sub.2 film and reaching a nonvolatile semiconductor memory cell during and after the formation of the contact hole.

Method for manufacturing contact hole for a nonvolatile semiconductor

A non-volatile semiconductor memory cell has a channel layer with a two-layered structure including a surface channel layer and a buried channel layer. The operation of reading out '1' level data or '0' level data from the memory cell is effected by using only the buried channel layer and based on whether the conductivity type of the buried layer is inverted or not. The operation of writing '0' level data is effected by using both of the surface channel layer and the buried channel layer, simultaneously inverting the conductivity types of the surface channel layer and the buried channel layer, and passing a current into the inverted layer to generate hot electrons.

Semiconductor device having a multi-layer channel structure

A semiconductor memory device includes a silicon chip, a memory cell transistor formed in the chip, a charge pump circuit formed in the chip, for boosting a source potential to generate a boosted potential, and a switching circuit formed in the chip. The switching circuit switches the portions to which the boosted voltage is supplied, depending on whether data is being written or erased. When writing data, the boosted potential is led to a drain of the memory cell transistor. When erasing data, the boosted potential is led to a source of the memory cell transistor.

Non-volatile semiconductor memory device with a small distribution width

A semiconductor memory device employing an element separating film, a conductive film, and an insulating film structure formed on a semiconductor substrate in this order. First side wall members are provided on the side surfaces of the element separating film, of the conductive film, and of the insulating film structure. A first gate electrode is formed on the insulating film structure, on the first side wall members, and on a first gate insulating film structure provided on the semiconductor substrate, adjacent to the first side wall members. A second gate insulating film structure is formed on the first gate electrode. Second side wall members are formed on the side surfaces of the second gate insulating film structure and of the first gate electrode. Contact holes are formed in the insulating film structure in a self-alignment manner by virtue of the second side wall members. A second gate electrode is formed on the inner peripheral surfaces of the contact holes, on the second side wall members, and on the second gate insulating film structure, such that the second gate electrode is connected to the conductive film through the contact holes.

Memory transistor having increased interelectrode capacitance

A floating gate is formed via a first gate insulating film over the channel region between source and drain regions which are formed in a semiconductor substrate. A control gate is formed via a second gate insulating film over the floating gate. A low impurity concentration semiconductor region is formed on the side of the control gate which faces the floating gate. When erasing, a depletion layer is produced in this low impurity concentration region and further saturates the erase characteristic for the erasure time by decreasing the capacitance between the control gate and the floating gate.

Non-volatile semiconductor memory having improved erasure characteristics

In a nonvolatile semiconductor memory device with a two-layer gate structure, an interlayer insulating film is formed on a floating gate electrode of, e.g., polycrystalline silicon. The interlayer insulating film has a four-layer structure in which a first silicon nitride film, a first silicon oxide film, a second silicon nitride film and a second silicon oxide film are laminated in this order on the floating gate electrode, or a two-layer structure in which a first silicon nitride film and a first silicon oxide film are laminated in this order on the floating gate electrode. With the above structure, the threshold voltage of the semiconductor device is stabilized even after data-erase operation. Since, moreover, the first silicon oxide film can be formed by oxidizing the first silicon nitride film, then the quality of the first silicon oxide film can be enhanced, and accordingly the charge retaining properties of the device can be increased.

Nonvolatile semiconductor device

A nonvolatile semiconductor device according to the present invention comprises a memory cell array having memory cells arranged in a matrix, each emory cell being composed of a floating gate electrode, control gate electrode, a source diffusion layer, and drain diffusion layer, tunnel oxide films formed on the side walls of the floating gate electrodes on the side where adjacent memory cells, sharing the control gate electrode, face each other, and an erasure gate electrode formed so as to sandwich the tunnel oxide films between the floating gate electrodes and itself, and electrically connected to the source diffusion layer at nearly an equal distance from the adjacent memory cells sharing the control gate electrode.

Electrically erasable memory device having erase-electrode connected to

A method of manufacturing a floating gate type nonvolatile memory cell having an offset region, wherein the length of the offset region is defined by the portion of the substrate covered by the injection blocking film formed on the side wall of the floating gate electrode. Thus, the offset region is self-aligned with respect to the side wall of the floating gate electrode. Moreover, since the insulating film formed on the floating gate electrode includes a nitride film, it is damaged little while the injection blocking film is being formed on or removed from the side wall of the floating gate electrode. In addition, when an oxide film is formed on the offset region, substantially no additional oxide film is formed on the nitride film in the insulating film on the floating gate electrode, and the thickness of the insulating film does not change.

Method of manufacturing a floating gate type nonvolatile memory cell

A source diffusion region and a drain diffusion region are formed under an insulation film which is thicker than a gate insulation film and which isolates the adjacent channel regions from each other. The adjacent source and drain diffusion regions are isolated from each other by a trench which extends from the central portion of the thick insulation film to the interior of a semiconductor substrate. The trench is formed in a self-alignment manner with reference to the end portions of the adjacent floating gate electrodes, and the depth of this trench is determined so that the adjacent source and drain diffusion regions can be spaced sufficiently apart from each other. Since the trench reliably prevents punch-through and current leakage to the adjacent element, it is possible to remarkably reduce the cell size. Moreover, the peripheral circuits are not complicated since the functions of the source and drain regions are fixed.

Nonvolatile semiconductor device with a trench isolator

Disclosed is a semiconductor device having a gate electrode consisting of a plurality of layers. The semiconductor device comprises a substrate, a first diffusion layer formed in the substrate, a second diffusion layer formed in the substrate, a floating gate electrode formed on a channel region between the first and second diffusion layers in an electrically floating state, and a control gate electrode formed on the floating gate electrode with an insulating film interposed therebetween. The first and second diffusion layers extend in parallel with each other along the longer side of the floating gate electrode. The control gate electrode extends in parallel with the shorter side of the floating gate electrode. The wiring layers for the first and second diffusion layers extend across the wiring layer for the control gate electrodes. Further, that portion of the first diffusion layer which is positioned adjacent to the floating gate electrode differs in impurity concentration from that portion of the second diffusion layer which is positioned adjacent to the floating gate electrode.

Semiconductor device having a gate electrode consisting of a plurality

A semiconductor memory device includes a first power source terminal supplied with a first power source voltage for data readout, a second power source terminal supplied with a second power source voltage for data write-in, memory cells formed of a floating gate type MOS transistor, a voltage switching circuit for selectively outputting one of the first and second power source voltages supplied to the first and second power source terminals, a voltage lowering circuit for lowering the second power source voltage supplied to the second power source terminal and outputting the lowered voltage, a gate potential control circuit connected to receive an output voltage of the voltage switching circuit as a power source voltage and supplies an output to the gate of the memory cell, and a drain potential control circuit connected to receive an output voltage of the voltage lowering circuit as a power source voltage and supplies an output to the drain of the memory cell. The second power source voltage for data write-in supplied to the second power source terminal is lowered by the power source voltage lowering circuit and is then supplied to the drain of the memory cell via the drain potential control circuit.

Growing community of inventors

Tokyo, Japan

Kuniyoshi Yoshikawa