Seiko Epson Corporation

Kunio Watanabe

Junichi Karasawa

Takashi Kumagai

Kazuo Tanaka

Masahiro Hayashi

Takahisa Akiba

Tomo Takaso

Susumu Kenmochi

Kazuhiko Okawa

Takahiko Yoshizawa

Takashi Sakuda

Masaki Okuyama

Takeshi Kumagai

Tatsuki Shirasawa

The manufacturing method of a semiconductor device can improve the mechanical strength of a pad more than before, and suppress the occurrence of a crack. The manufacturing method of a semiconductor device includes: forming a first pad constituted by a first metal layer; forming an insulating layer on the first pad; providing an opening portion in the insulating layer by removing the insulating layer on at least a partial region of the first pad; forming a second pad constituted by a second metal layer in the opening portion of the insulating layer so as to have a film thickness that is smaller than the film thickness of the insulating layer; and forming a third pad constituted by a third metal layer on the second pad.

Semiconductor device and manufacturing method thereof

A semiconductor device includes: a memory transistor including a first silicon oxide film, a first silicon nitride film, a second silicon oxide film, and a first gate electrode that are disposed in sequence on a substrate; and a MOS transistor including a third silicon oxide film and a second gate electrode that are disposed in sequence on the substrate. The memory transistor has a side wall including an extending portion of the first silicon oxide film, a second silicon nitride film that is in contact with the first silicon nitride film, and a fourth silicon oxide film that are disposed in sequence on the substrate, and the MOS transistor has a side wall including a fifth silicon oxide film that is disposed on the substrate.

Semiconductor device and production method thereof

A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.

Semiconductor device

A semiconductor device may include a fuse sectionhaving a layer in which a plurality of fusesthat are fusible by irradiation of an energy beam are formed, and a circuit wiring layerformed in the fuse sectionThe circuit wiring layeris disposed in a layer below the layer in which the fusesare formed, and is not connected to the fuses

Semiconductor devices including fuses and dummy fuses

A semiconductor device is provided with an SRAM memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and second drain-gate wiring layers. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively. A first protruded active region is provided in a manner to protrude from an end portion of the first active region.

Semiconductor device having a protruded active region, memory system having the same, and electronic apparatus having the same

A semiconductor device is provided with a memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and a second drain-gate wiring layer. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively.

Semiconductor device, memory system and electronic apparatus

A semiconductor memory device has a peripheral circuit area and a memory cell area on a main surface thereof. The semiconductor memory device includes a first well formed in the peripheral circuit area, a second well of a first conductivity type formed in the memory cell area, a third well of a second conductivity type formed in the memory cell area, and a device isolation structure formed in the memory cell area for isolating an element formed in the second well from an element formed in the third well. The second well of the first conductivity type has a depth shallower than a depth of the first well. The third well of the second conductivity type is equal in depth to the second well. The second and third wells are formed down to a level lower than the device isolation structure.

Semiconductor memory device and method for manufacturing the same

A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes first and second gate&mdash;gate electrode layers, first and second drain&mdash;drain wiring layers, and first and second drain-gate wiring layers. The first drain-gate wiring layer and the second drain-gate wiring layer are located in different layers. The first drain-gate wiring layer is located below the first drain&mdash;drain wiring layer, and the second drain-gate wiring layer is located in above the first drain&mdash;drain wiring layer. This structure provides a semiconductor device that has reduced cell area. The invention also provides a memory system and electronic apparatus that include the above semiconductor device.

Semiconductor devices are provided that include a memory cell having load transistors, driver transistors, and transfer transistors. The semiconductor device has a first element-forming region that can be provided in, for example, a p-well region. The first element-forming region can include includes a first active region, a second active region, a third active region, a fourth active region and a fifth active region. The third active region, the fourth active region and the fifth active region can be provided between the first active region and the second active region. The first active region and the second active region can be continuous with the third active region, the fourth active region and the fifth active region, respectively. Thus, semiconductor devices can be provided having element-forming regions that can be readily formed. Memory systems and electronic equipment that include such semiconductor devices can also be provided.

Semiconductor devices, memory systems and electronic apparatuses with improved latch up suppression

A semiconductor device is provided with a memory cell. The semiconductor device includes a first gate&mdash;gate electrode layer, a second gate&mdash;gate electrode layer, a first drain&mdash;drain wiring layer, a second drain&mdash;drain wiring layer, a first drain-gate wiring layer and second drain-gate wiring layers. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively. The width of the first gate&mdash;gate electrode layer in the first load transistor is larger than the width of the first gate&mdash;gate electrode layer in the first driver transistor.

A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes a first gate-gate electrode layer and a first drain-gate wiring layer. A distance L between the edges of the first drain-gate wiring layer and an active region of the first driver transistor is greater than or equal to a distance L between the first drain-gate wiring layer and an active region of the first load transistor. This structure provides semiconductor devices in which memory cells having desired characteristics can be readily fabricated. The invention also provides memory systems and electronic apparatuses which include the above semiconductor devices.

A semiconductor memory device (SRAM) comprises memory cells, each of which includes two load transistors, two driver transistors and two transfer transistors. The SRAM cell includes a semiconductor substrate in which the transistors are formed, a first interlayer dielectric formed on the semiconductor substrate, first contact portions formed in the first interlayer dielectric and first wiring layers (node wiring layers and pad layers) formed on the first interlayer dielectric. The first contact portions and the first wiring layers include metal layers made of refractory metal and a refractory metal nitride layers. This semiconductor memory device of the present invention is capable of enhancing an integration degree of wiring layers and achieving a microfabrication.

Semiconductor memory device and method of fabricating the same

A semiconductor device has a semiconductor substrate having a peripheral circuit area and a memory cell area. A border region having a well of a first conductivity is formed between the peripheral circuit area and the memory cell area. A well of a second conductivity is formed in the peripheral circuit area. The well in the peripheral circuit area is in contact with the border region but not in contact with the memory cell area. Dummy transistors are formed in the border region. The dummy transistors are arranged with substantially the same transistor forming density as that of the memory cell area.

Growing community of inventors

Sakata, Japan

Kunio Watanabe