Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Vlsi Engineering Corp.

Other

Renesas Electronics Corporation

Hitachi Micro Systems, Inc.

Hitachi Ulsi Systems Co., Ltd.

Hitachi America, Ltd.

Renesas Technology America, Inc.

Hitachi Microcomputer Eng. Ltd.

Hitachi Microcomputer

Kunio Uchiyama

Osamu Nishii

Tadahiko Nishimukai

Takayuki Kawahara

Masakazu Aoki

Kiyoo Itoh

Masashi Horiguchi

Takeshi Sakata

Atsushi Hasegawa

Makoto Hanawa

Susumu Narita

Hirokazu Aoki

Ikuya Kawasaki

Norio Nakagawa

Koichiro Ishibashi

Kanji Oishi

Hiroyuki Mizuno

Fumio Arakawa

Susumu Hatano

Takashi Kikuchi

Yasuhiko Saigou

Prasenjit Biswas

Hiroshi Fukuta

Ryoichi Hori

Kevin Ray Iadonato

Ryoichi Kurihara

Takanori Shimura

Yonetaro Totsuka

Gautam Dewan

Asako Sekine

Yoichi Katsuki

Kenichi Osada

Shuji Ikeda

Masayuki Sato

Yasuhisa Shimazaki

Masayuki Kojima

Yasuko Yoshida

Mitsuyuki Kimura

Kenji Shiozawa

Takao Watanabe

Masayuki Miyazaki

Masaru Kokubo

Katsuyuki Sato

Junichi Nishimoto

Naohiko Irie

Masayuki Ito

Kiyoshi Hasegawa

Kiwamu Takada

Ken Tatezawa

Makoto Toda

Yoshifumi Takamoto

Yoshinobu Nakagome

Goro Kitsukawa

Takeshi Aimoto

Masayuki M Nakamura

Yoshimune Hagiwara

Tetsuhiko Okada

Noboru Yamaguchi

Shumpei Kawasaki

Haruo Koizumi

Jun Kitano

The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

Substrate bias switching unit for a low power processor

A processor system including: a processor having a processor core and a controller core; and a plurality of synchronous memory chips, wherein the processor and the plurality of synchronous memory chips are connected via an external bus; wherein the processor core and the controller core are connected via an internal bus; wherein the plurality of synchronous memory chips are operated according to a clock signal; wherein the controller core comprises a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.

Processor system using synchronous dynamic memory

A processor system including: a processor and controller core connected via an internal bus; and a plurality of synchronous memory chips connected to the processor via an external bus; the controller core including a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.

A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Semiconductor integrated circuit device having power reduction mechanism

A chip including: a microprocessor; a control unit coupled to the microprocessor; and interface nodes for coupling a synchronous dynamic memory; wherein the control unit generates command information and the interface nodes output the command information to the synchronous dynamic memory in synchronism with a clock signal, wherein the command information includes a mode register set function which sets mode information to a mode register in the synchronous dynamic memory, and wherein the control unit outputs the mode information to address signal input terminals of the synchronous dynamic memory.

When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

Semiconductor device

An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

Floating point unit pipeline synchronized with processor pipeline

A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

A semiconductor integrated circuit device is composed of logic gates each provided with MOS transistors. The semiconductor integrated circuit device includes a current control device. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors, that have both an operation mode and a low power back-up or sleep mode used for power reduction.

A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock signal generating circuits having different clock-settling times and the selection thereof is effected from outside of the device. A first one of the clock signal generating circuits uses, for example, a phase-locked loop circuit which has a large clock-settling time, and the second clock signal generating circuit is implemented, for example, using a delay-locked loop circuit whose clock-settling time is small, for example, 2-3 periods. Due to the selective actuation of the second clock signal generating circuit, which has a small clock-settling time, the generating of clock signals for the internal circuits can also be halted when the internal circuits of the device are halted thereby to further lower power consumption without compromising clock oscillator responsiveness.

Semiconductor integrated circuit device

A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the instruction address, an instruction decoder decoding an instruction from said cache memory corresponding to an instruction address from said instruction address generator, an operand address generator generating an operand address in response to an output signal of said instruction decoder, and an operand cache memory having entries each storing an operand address and operand data corresponding to the operand address in its entry. The data processor executes an instruction that makes entries in both of said instruction cache memory and said operand cache memory ineffective.

Data processor capable of executing an instruction that makes a cache memory ineffective

Growing community of inventors

Kodaira, Japan

Kunio Uchiyama