Altera Corporation

Kunio Nishiwaki

Kevin A Norman

Krishna Rangasayee

Brad Ishihara

A method of programming and verifying a macroscale based architecture in a field programmable logic device includes the step of selecting a flip-flop. The flip-flop contains a programmable address that accepts a sequence of instructions. A Switch Controller then selectably enables either one of two banks of switches. If the first bank of switches is selected, the programming operation is selected. If the second bank of switches is enabled, the verification operation is selected. The verification operation includes the step of automatically incrementing a base address through a set of incremented addresses. For each incremented address produced by the incrementing step, a margin low operation is performed with a Level Tester Array and a margin high operation is performed with a Level Tester Array. Thus, unlike the prior art, margin operations with the present invention are performed without using a macrocell scan register. Advantageously, relatively large groups of data are loaded into the flip-flops in the ADSR to improve processing.

Apparatus and method for verifying macrocell base field programmable logic devices

A sense amplifier for detecting the voltage state (high or low) of the bit line of a programmable logic device with improved switching speed when the voltage state changes. When the bit line is high, a pull-up circuit including a cascode limits the maximum bit line voltage while isolating the output node from a supply of positive potential. At the same time, a transistor turned on by the high bit line voltage connects the output node to ground. An inverting amplifier on the output node produces an amplified output that follows the bit line. When the bit line is low, the conductance of a transistor gated by the bit line is substantially reduced, resulting in a relatively small conductance between the source line and ground, so that the source line potential rises significantly. The relatively large conductance between the bit line and source line as compared to the relatively small conductance between the source line and ground causes the potentials on the bit line and source line to approach one another and stabilize at a potential significantly above ground potential, so that the minimum voltage level on the bit line is also limited. The voltage on the bit line in the low state is too low to activate the transistors that connect the output node to ground, but it does activate a transistor that connects the output node to the supply of positive potential, pulling the output node high and the inverted amplified output low.

Sense amplifier for programmable logic device

A circuit and method for generating a reference voltage which decreases as a supply voltage increases, and increases as the supply voltage decreases are provided. The circuit includes a voltage divider connected to the input of an inverting amplifier whose output is connected to a level shifter/buffer. Increases in the supply voltage cause the output voltage of the voltage divider and hence the input voltage of the inverting amplifier to increase. Over the operating range, the combined effect of the increasing input and supply voltage cause the output voltage of the inverting amplifier to decrease. Similarly, over the operating range, a decrease in supply voltage causes an increase in output voltage from the inverting amplifier. This output voltage is shifted to a level more convenient for the user by the level shifter/buffer. The buffer also increases the amount of output current that can be supplied by the reference voltage generator.

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San Jose, CA, United States of America

Kunio Nishiwaki