Kabushiki Kaisha Toshiba

Kunio Muramatsu

Seigo Suzuki

An A/D converter and a method of testing the same. Resistors R1 to Rn are connected in series between power-supply terminals receiving a high potential and a low potential, respectively. The potentials at the nodes of the resistors R1 to Rn are input to voltage comparators C1 to Cn-1, respectively. Each comparator compares the input potential with an input signal Vin. The output signals of comparator is supplied to an encoder. The encoder converts the input signals into a digital signal. A test terminal is connected to one of the nodes of the resistors R1 to Rn. Either the high potential at the terminal or the low potential at the terminal is applied to the test terminal to test the A/D converter.

A/D converter using resistor ladder network and method of testing the

A line memory for speed conversion, whose data rates of write into and read from a memory cell (1) differ from each other, has a write circuit (2, 3, 4) for writing input data (D.sub.in) into the cell (1) at a predetermined rate and resetting the write address of the cell (1) at a predetermined period, a read circuit (5, 6, 7) for reading data (D.sub.out) from cell (1) at a rate different from the write rate and resetting the read address of the cell (1) at the predetermined period, the first shift circuit (8) for shifting reset timing of the write address, and the second shift circuit (9) for shifting reset timing of the read address, the first and second shift circuits enabling respective setting quantities at the same value. This memory can shift both the write address reset timing and the read address reset timing while keeping both in the same condition.

Growing community of inventors

Fujisawa, Japan

Kunio Muramatsu