Nec Corporation

Nec Electronics Corporation

Renesas Electronics Corporation

Kuniko Kikuta

Makoto Nakayama

Ryota Yamamoto

Masayuki Furumiya

Masato Kawata

Yasutaka Nakashiba

Hiroaki Ohkubo

Naoki Oda

Hiroshi Murase

Tokuhito Sasaki

Nobukazu Ito

Naoyoshi Kawahara

Kazuyuki Hirose

Masaharu Sato

Kenichi Shimura

Takeshi Okazawa

Kiyotaka Tsuji

A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

Semiconductor device including metal-insulator-metal capacitor arrangement

In a temperature sensor section of a semiconductor integrated circuit device, wires of the topmost wiring layer of a multi-layer wiring structure are formed. A sheet-like temperature monitor element of vanadium oxide is provided between two of the wires in such a way as to cover the two wires. Accordingly, the temperature monitor element is connected between the two wires of an underlying wiring layer of the multi-layer wiring structure through two vias and the two wires of the topmost wiring layer.

Integrated circuit device and fabrication method therefor

A semiconductor device includes a capacitor with an MIM structure, by which the dimensional accuracy of the device is improved, and a stable capacitance value is given. The semiconductor deviceincludes: a semiconductor substrate; a capacitor forming regionin which an MIM capacitor is formed, which has an insulating interlayerformed on the semiconductor substrate, a first electrode, and a second electrode, and the first electrodeand the second electrodeare arranged facing each other through the insulating interlayer; and a shielding regionwhich includes a plurality of shielding electrodesformed in the outer edge of the capacitor forming regionand, at the same time, set at a predetermined potential in the same layer as that of the MIM capacitor on the semiconductor substrate, and shields the capacitor forming regionfrom other regions.

Semiconductor device

An N-type deep well is used to protect a circuit from a noise. However, a noise with a high frequency propagates through the N-type deep well, and as a result, the circuit that should be protected malfunctions. To reduce the area of the N-type deep well. For instance, in the present invention, a semiconductor device comprises a semiconductor substrate of a first conductivity type, a digital circuit part and an analog circuit part provided on the semiconductor substrate, a plurality of wells of the first conductivity type formed in either the analog circuit part or the digital circuit part, and a first deep well of a second conductivity type, which is the opposite conductivity type to the first conductivity type, isolating some of the plurality of wells from the semiconductor substrate.

Semiconductor device having analog and digital circuits

A method for manufacturing a semiconductor device is provided. The method includes forming a lower interconnection on a semiconductor substrate; forming a first interlayer insulation film in which the lower interconnection is buried; forming an MIM capacitive element on the first interlayer insulation film, the MIM capacitive element being formed by layering a lower electrode, a dielectric film, and an upper electrode; forming a second interlayer insulation film in which the MIM capacitive element is buried; forming via holes in the second interlayer insulation film so as to reach the lower electrode; forming a connection plug by filling the via hole with conductive film; and forming an upper interconnection to be connected to the connection plug above the second interlayer insulation film.

Semiconductor device having MIM capacitive elements and manufacturing method for the same

A technique for reducing influences of the bias magnetic field developed by yokes used for concentrating the magnetic field on magnetoresistance elements, on MRAM operations. An MRAM is composed of a plurality of magnetoresistance elements having magnetic anisotropy in a first direction; a wiring extended in a second direction different from the first direction, through which a write current flows for writing data into the magnetoresistance elements; and a yoke layer formed of ferromagnetic material, extended along the second direction, and covering at least a portion of a surface of the wiring. The plurality of magnetoresistance elements include a first magnetoresistance element, and a second magnetoresistance element of which the distance from an end of the yoke layer is further than that of the first magnetoresistance element. The first magnetoresistance element has a magnetic anisotropy stronger than that of the second magnetoresistance element.

Magnetic random access memory

On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.

Semiconductor device and fabrication method thereof

In a temperature sensor section of a semiconductor integrated circuit device, first vias of tungsten are formed at the topmost layer of a multi-layer wiring layer and pads of titanium are provided on regions of the multi-layer wiring layer which covers the vias. An insulating layer is provided in such a way as to cover the multi-layer wiring layer and the pads, second vias are so formed as to reach the pads. Vanadium oxide is buried in the second vias by reactive sputtering, and a temperature monitor part of vanadium oxide is provided in such a way as to connect the second vias each other. Accordingly, the temperature monitor part is connected between the two wires.

Integrated circuit device

A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and includes a lower electrode, an upper electrode, and a dielectric film sandwiched therebetween. An upper interconnection is provided on a second interlayer insulation film in which the MIM capacitive element is buried. A contact electrically connects the lower electrode and the upper interconnection. The lower electrode is mainly formed of Al, so that they are lower in electrical resistance than barrier metal, and also low in stress value. Therefore, it becomes possible to widen the area of the lower electrode for electrically connecting the contact while restraining their influences on charge accumulation and close contact between the lower electrode and the insulation film. In addition, since the electrical resistance is lowered, the thickness of the lower electrode can be increased. Accordingly, the MIM capacitive element with a large capacitance can be manufactured with a high yield.

Semiconductor device and manufacturing method for the same

As for the resistor on the semiconductor substrate, it is required to achieve obtaining a metal resistor, which can be formed in the latter half of a preliminary process for manufacturing a semiconductor, in addition to forming a polysilicon resistor, which is formed in the first half of the preliminary process. A capacitor having MIM structure comprises a lower electrode, a capacitive insulating film and an upper electrode, all of which are sequentially formed in this sequence. A resistor structure having MIM structure also comprises a lower electrode, a capacitive insulating film and a resistor, all of which are sequentially formed in this sequence. In this case, the biasing conditions thereof should be selected so that the resistor structure lower electrode of the MIM structure resistor is not coupled to any electric potential, and is in a floating condition. Therefore, even if the signal of higher frequency is applied to the metal resistor, the resistor structure lower electrode is hardly affected by the parasitic capacitance thereof due to its floating condition, thereby providing improved high frequency characteristics of the device including such metal resistor.

Semiconductor device having MIM structure resistor

The present invention provides an electrically conductive layer comprising a copper alloy which includes at least one of Ag, As, Bi, P, Sb, Si, and Ti in the range of not less than 0.1 percent by weight to not more than a maximum solubility limit to copper, so that the copper alloy is in a solid solution and/or which includes at least one of Mo, Ta and W in a range of not less than 0.1 percent by weight to not more than 1 percent by weight.

Copper-alloy interconnection layer

A magnetic memory of a present invention is formed as below. The magnetic memory has a TMR film formed on a first conductive film, and a second conductive film with a flat top surface, having the same plane shape as that of the TMR film, formed on the TMR laminated film. A first insulating film having a flat top surface and the same height as the surface of the second conductive film is formed so as to surround the TMR film and the second conductive film. A third conductive film connected electrically to the second conductive film is formed on the first insulating film.

Magnetic memory and method of its manufacture

In a non-volatile semiconductor memory having a peripheral circuit zone and a memory zone including plural memory cells each having a floating gate and a control gate, an interlayer insulator is formed over the control gate of the memory cells and a gate electrode in the peripheral circuit zone. A groove is formed in the interlayer insulator film to longitudinally extend along a word line which constitutes the control gate for a plurality of memory cells arranged in one line. This groove penetrates through the interlayer insulator film to reach the word line over the whole length of the word line. A conducting material is deposited on the interlayer insulator film to fill up the groove so that a plate-shaped contact is formed in the groove. The conducting material is patterned to form an overlying interconnection extending on the interlayer insulator film along the word line.

Growing community of inventors

Kanagawa, Japan

Kuniko Kikuta