National Institute of Advanced Industrial Science and Technology

Agency of Industrial Science and Technology

Kunihiro Sakamoto

Shinichi Ouchi

Yongxun Liu

Meishoku Masahara

Kazuhiko Endo

Takashi Matsukawa

Atsushi Ando

A manufacturing method of the nano-wire field effect transistor, comprising steps of preparing an SOI substrate having a (100) surface orientation; processing a silicon crystal layer comprising the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal layer by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other so as to face along the ridge lines of the triangular columnar members; and processing the two triangular columnar members into a circular columnar member configuring a nano-wire by hydrogen annealing or thermal oxidation.

Nano-wire field effect transistor, method for manufacturing the transistor, and integrated circuit including the transistor

Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor.

A method for surface flattening a crystal substrate includes (a) processing a surface of a silicon single crystal substrate, the surface deviating by 0.1.degree. or less from the (001) plane, so as to form a processed zone thereon which is an obstacle to the movement of surface steps present on the surface of the silicon single crystal substrate and which is adjacent to a preselected region having a surface to be flattened when viewed on an atomic level; (b) holding the substrate processed in step (a) in a chamber having an adjustable degree of vacuum so that the substrate has a temperature which is controlled by direct-current passage and heating; and (c) heating the substrate to move the surface steps along the substrate from the preselected region and gather the surface steps in the processed zone, thereby forming a flat surface in the preselected region of the substrate when viewed on the atomic level. In one embodiment, the direction of direct-current passage is displaced from the �1 1 0! and �1 1 0! directions, whereby the surface of the preselected region is flattened in all directions of the substrate surface.

Growing community of inventors

Tsukuba, Japan

Kunihiro Sakamoto