Fujitsu Semiconductor Limited

Fujitsu Corporation

Fujitsu Microelectronics Limited

Kunihiro Ohara

Tomohiro Fukuoka

Kazuya Taniguchi

Yukisato Miyazaki

Hiroshi Naritomi

Masayuki Takeshige

Hayato Isobe

Sumitaka Hibino

Teruyoshi Kondo

Aspects of an embodiment include providing a correction circuit that corrects image data in apiece of a frame, the correction circuit comprising: a weight processing unit which performs weighting on position data corresponding to a relative position in response to the relative position between a position of a pixel in the image data and a certain position in the frame; and a correction processing unit that corrects the image data based on a correction value corresponding to the weighted position data.

Correction circuit, correction method and image pickup apparatus

An object of the present invention is to provide an image data processing circuit and an image data processing method capable of determining a reference signal level corresponding to black in an image with high precision by suppressing occurrence of line dependency and the like in a dark current component signal included in image data output from a solid state image pickup device. A reference dark current component data holding unit selects a reference line from a solid state image pickup device and holds a dark current component of the reference line as a head line average value. To a subtraction circuit, dark current component data and effective pixel data is sequentially input on the line unit basis. A differential circuit obtains, as a detection value, a change amount with respect to the head line average value, of the dark current component data included in a preceding line. The subtraction circuit subtracts the detection value from the dark current component data and the effective pixel data entered.

Image data processing circuit and image data processing method

A shading compensation circuit is provided which is capable of storing correction coefficients for shading compensation having optimal bit lengths, so that the data size of the correction coefficients can be reduced. The shading compensation circuitfor correcting the shading properties with respect to a horizontal direction and a vertical direction, has horizontal correction coefficient HHK and vertical correction coefficient VHK each having a bit length optimized according to a horizontal direction counter value HCT or a vertical direction counter value VCT. The horizontal and vertical correction coefficients HHK, VHK for the periphery of the image data are longer in bit length than the correction coefficients HHK, VHK for the center of the image data.

Shading compensation circuit and control method thereof

An object is to provide an image processing circuit and an image processing method which can use various technologies for a bayer array CCD even when an RGB independent array CCD is used, and can accommodate for the bayer array CCD. A first matrix acquiring circuitG acquires an R signal for each basic matrix, and a first averaging circuitG outputs an average value AveCHof the R signal. Similarly, a second matrix acquiring circuitG acquires a G signal, and a second averaging circuitG outputs an average value AveCHof the G signal. Further, similarly, a third matrix acquiring circuitG acquires a B signal, and a third averaging circuitG outputs an average value AveCHof the B signal. A data array conversion circuitG converts the average values AveCHthrough AveCHinto a conversion matrix of two pixels&#xd7;two pixels in bayer array. The conversion matrix is detected by a detection circuitfor bayer array.

Image processing circuit and image processing method

A serial data receiving circuit and a serial data receiving method are provided which are capable of performing interconversion on bit sequences of data bit groups, between LSB first and MSB first, in serial data transmitted serially in successive data bit groups. Conversion parts Cthrough Creceive 8 different bit strings BSthrough BShaving a 32-bit bit length and in which a start position of a head bit is shifted by one bit at a time. Conversion parts Cthrough Cperform a conversion operation to reverse a bit sequence of the bit strings BSthrough BSevery 8 bits starting from a head bit. Coincidence detection circuits Dthrough Dperform coincidence detection on the bit strings BSthrough BSto detect coincidence with a synchronization pattern RS. A selector circuitextracts any of upper bit strings HCBSthrough HCBSfrom the bit strings on which coincidence detection was performed, and outputs the result as detection data FD.

Serial data receiving circuit and serial data receiving method

A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores the lower order bits in a lower order bit storage section and the higher order bits in a higher order bit storage section. The lower order bits and the corresponding higher order bits are read from the memory in the same cycle when generating the instruction code.

Method and apparatus for compactly storing instruction codes

A bus controller for a CCD digital still camera arbitrates competing requests by multiple microcontrollers for a shared memory. One of the microcontrollers is designated to have a higher priority than the other microcontroller(s). In the case of competing requests, while one microcontroller is granted access to the memory, the other microcontroller performs other processing, and polls a memory status register to determine when the memory is available. Since the waiting processor performs other operations, as opposed to idling, the efficiency of the microcontroller is improved.

Growing community of inventors

Kasugai, Japan

Kunihiro Ohara